rtl8188e/usb/r88eu_init.c

57 r88eu_init_bb(struct rtwn_softc *sc)
61 	rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
65 	rtwn_write_1(sc, R92C_RF_CTRL,
67 	rtwn_write_1(sc, R92C_SYS_FUNC_EN,
71 	r88e_init_bb_common(sc);
75 r88eu_power_on(struct rtwn_softc *sc)
85 		if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
87 		rtwn_delay(sc, 10);
90 		device_printf(sc->sc_dev,
96 	RTWN_CHK(rtwn_setbits_1(sc, R92C_SYS_FUNC_EN,
99 	RTWN_CHK(rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80));
102 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
106 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
109 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
112 		if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
115 		rtwn_delay(sc, 10);
121 	RTWN_CHK(rtwn_setbits_1(sc, R92C_LPLDO_CTRL,
125 	RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0));
126 	RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
130 	    ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
138 r88eu_power_off(struct rtwn_softc *sc)
144 	error = rtwn_setbits_1(sc, R88E_TX_RPT_CTRL,
150 	rtwn_write_1(sc, R92C_CR, 0);
154 	rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
158 		if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
161 		rtwn_delay(sc, 5000);
164 		device_printf(sc->sc_dev, "%s: failed to block Tx queues\n",
170 	rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
172 	rtwn_delay(sc, 1);
175 	rtwn_write_1(sc, R92C_CR,
181 	rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
184 	rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, 0x20);
188 	if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY)
189 		r88e_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN);
193 	rtwn_write_1(sc, R92C_MCUFWDL, 0);
196 	rtwn_setbits_1(sc, R88E_32K_CTRL, 0x01, 0);
200 	rtwn_write_1(sc, R92C_RF_CTRL, 0);
203 	rtwn_setbits_1(sc, R92C_LPLDO_CTRL, 0, R92C_LPLDO_CTRL_SLEEP);
206 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
211 		if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
215 		rtwn_delay(sc, 5000);
218 		device_printf(sc->sc_dev, "%s: could not turn off MAC\n",
224 	rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80);
227 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
231 	rtwn_write_1(sc, R92C_APS_FSMCO + 3, 0);
234 	rtwn_setbits_1(sc, R92C_GPIO_MUXCFG + 1, 0x10, 0);
237 	rtwn_setbits_1(sc, R92C_USB_SUSPEND, 0, 0x10);
240 	reg = rtwn_read_1(sc, R92C_RSV_CTRL + 1);
241 	rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08);
242 	rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08);
245 	rtwn_write_1(sc, R92C_GPIO_OUT, rtwn_read_1(sc, R92C_GPIO_IN));
246 	rtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff);
248 	rtwn_write_1(sc, R92C_GPIO_IO_SEL,
249 	    rtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4);
250 	rtwn_setbits_1(sc, R92C_GPIO_MOD, 0, 0x0f);
253 	rtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808);
257 r88eu_init_intr(struct rtwn_softc *sc)
260 	rtwn_write_4(sc, R88E_HISR, 0xffffffff);
261 	rtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 |
263 	rtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW |
265 	rtwn_setbits_1(sc, R92C_USB_SPECIAL_OPTION, 0,
270 r88eu_init_rx_agg(struct rtwn_softc *sc)
273 	rtwn_setbits_1(sc, R92C_TRXDMA_CTRL, 0,
276 	rtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48);
277 	rtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4);
281 r88eu_post_init(struct rtwn_softc *sc)
285 	rtwn_setbits_1(sc, R88E_TX_RPT_CTRL, 0, R88E_TX_RPT1_ENA);
288 	rtwn_write_4(sc, R88E_MACID_NO_LINK, 0xffffffff);
289 	rtwn_write_4(sc, R88E_MACID_NO_LINK + 4, 0xffffffff);
290 	r88e_macid_enable_link(sc, RTWN_MACID_BC, 1);
293 	r88e_iq_calib(sc);
295 	r92c_lc_calib(sc);
297 	rtwn_write_1(sc, R92C_USB_HRPWM, 0);
299 	if (sc->sc_ratectl_sysctl == RTWN_RATECTL_FW) {
301 		sc->sc_ratectl = RTWN_RATECTL_NET80211;
303 		sc->sc_ratectl = sc->sc_ratectl_sysctl;