rtl8188e/pci/r88ee_init.c

57 r88ee_init_bb(struct rtwn_softc *sc)
61 	rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
65 	rtwn_write_1(sc, R92C_RF_CTRL,
67 	rtwn_write_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_PPLL |
71 	r88e_init_bb_common(sc);
75 r88ee_init_intr(struct rtwn_softc *sc)
78 	rtwn_write_4(sc, R88E_HIMR, 0x00000000);
79 	rtwn_write_4(sc, R88E_HIMRE, 0x00000000);
83 r88ee_power_on(struct rtwn_softc *sc)
88 	rtwn_setbits_1(sc, R88E_XCK_OUT_CTRL, R88E_XCK_OUT_CTRL_EN, 0);
91 	rtwn_setbits_2(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_APDM_HPDN, 0);
92 	rtwn_write_1(sc, R92C_RSV_CTRL, 0);
96 		if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
98 		rtwn_delay(sc, 10);
101 		device_printf(sc->sc_dev,
107 	rtwn_setbits_1(sc, R92C_SYS_FUNC_EN,
111 	rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80);
114 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
118 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
122 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
125 		if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
128 		rtwn_delay(sc, 10);
133 	rtwn_setbits_1(sc, R92C_PCIE_CTRL_REG + 2, 0, 0x04);
136 	rtwn_setbits_1(sc, R92C_LPLDO_CTRL, R92C_LPLDO_CTRL_SLEEP, 0);
138 	rtwn_setbits_1(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_PDN_EN);
139 	rtwn_setbits_1(sc, R92C_PCIE_CTRL_REG + 2, 0, 0x04);
140 	rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL_EXT + 1, 0, 0x02);
141 	rtwn_setbits_1(sc, R92C_SYS_CLKR, 0, 0x08);
142 	rtwn_setbits_2(sc, R92C_GPIO_MUXCFG, R92C_GPIO_MUXCFG_ENSIC, 0);
145 	rtwn_write_2(sc, R92C_CR, 0);
146 	rtwn_setbits_2(sc, R92C_CR, 0,
150 	    ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
153 	rtwn_write_4(sc, R92C_INT_MIG, 0);
154 	rtwn_write_4(sc, R92C_MCUTST_1, 0);
160 r88ee_power_off(struct rtwn_softc *sc)
166 	rtwn_setbits_1(sc, R88E_TX_RPT_CTRL,
169 	rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 1, 0xFF);
173 	rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
177 		if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
180 		rtwn_delay(sc, 5000);
183 		device_printf(sc->sc_dev, "%s: failed to block Tx queues\n",
189 	rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
191 	rtwn_delay(sc, 1);
194 	rtwn_write_1(sc, R92C_CR,
200 	rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
203 	rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, 0x20);
207 	if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY)
208 		r88e_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN);
212 	rtwn_write_1(sc, R92C_MCUFWDL, 0);
215 	rtwn_setbits_1(sc, R88E_32K_CTRL, 0x01, 0);
219 	rtwn_write_1(sc, R92C_RF_CTRL, 0);
222 	rtwn_setbits_1(sc, R92C_LPLDO_CTRL, 0, R92C_LPLDO_CTRL_SLEEP);
225 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
230 		if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
234 		rtwn_delay(sc, 5000);
237 		device_printf(sc->sc_dev, "%s: could not turn off MAC\n",
243 	rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80);
246 	reg = rtwn_read_1(sc, R92C_RSV_CTRL + 1);
247 	rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08);
248 	rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08);
251 	rtwn_write_1(sc, R92C_GPIO_OUT, rtwn_read_1(sc, R92C_GPIO_IN));
252 	rtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff);
254 	rtwn_write_1(sc, R92C_GPIO_IO_SEL,
255 	    rtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4);
256 	rtwn_setbits_1(sc, R92C_GPIO_MOD, 0, 0x0f);
259 	rtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808);
263 r88ee_post_init(struct rtwn_softc *sc)
267 	rtwn_setbits_1(sc, R88E_TX_RPT_CTRL, 0, R88E_TX_RPT1_ENA);
270 	rtwn_write_4(sc, R88E_MACID_NO_LINK, 0xffffffff);
271 	rtwn_write_4(sc, R88E_MACID_NO_LINK + 4, 0xffffffff);
272 	r88e_macid_enable_link(sc, RTWN_MACID_BC, 1);
275 	r88e_iq_calib(sc);
277 	r92c_lc_calib(sc);
280 	rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 1, 0);
282 	if (sc->sc_ratectl_sysctl == RTWN_RATECTL_FW) {
284 		sc->sc_ratectl = RTWN_RATECTL_NET80211;
286 		sc->sc_ratectl = sc->sc_ratectl_sysctl;