dev/ral/rt2661.c

243 		error = rt2661_alloc_tx_ring(sc, &sc->txq[ac],
325 		rt2661_free_tx_ring(sc, &sc->txq[ac]);
343 	rt2661_free_tx_ring(sc, &sc->txq[0]);
344 	rt2661_free_tx_ring(sc, &sc->txq[1]);
345 	rt2661_free_tx_ring(sc, &sc->txq[2]);
346 	rt2661_free_tx_ring(sc, &sc->txq[3]);
853 	struct rt2661_tx_ring *txq;
869 		txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq;
872 		data = &txq->data[txq->stat];
912 		DPRINTFN(sc, 15, "tx done q=%d idx=%u\n", qid, txq->stat);
914 		txq->queued--;
915 		if (++txq->stat >= txq->count)	/* faster than % count */
916 			txq->stat = 0;
927 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq)
932 	bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD);
935 		desc = &txq->desc[txq->next];
936 		data = &txq->data[txq->next];
942 		bus_dmamap_sync(txq->data_dmat, data->map,
944 		bus_dmamap_unload(txq->data_dmat, data->map);
949 		DPRINTFN(sc, 15, "tx dma done q=%p idx=%u\n", txq, txq->next);
951 		if (++txq->next >= txq->count)	/* faster than % count */
952 			txq->next = 0;
955 	bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1157 		rt2661_tx_dma_intr(sc, &sc->txq[0]);
1160 		rt2661_tx_dma_intr(sc, &sc->txq[1]);
1163 		rt2661_tx_dma_intr(sc, &sc->txq[2]);
1166 		rt2661_tx_dma_intr(sc, &sc->txq[3]);
1363 	struct rt2661_tx_ring *txq = &sc->txq[ac];
1379 	data = &txq->data[txq->cur];
1380 	desc = &txq->desc[txq->cur];
1382 	error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, mprot, segs,
1404 	bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1405 	bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1407 	txq->queued++;
1408 	txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT;
1419 	struct rt2661_tx_ring *txq = &sc->txq[ac];
1477 	data = &txq->data[txq->cur];
1478 	desc = &txq->desc[txq->cur];
1480 	error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs,
1498 		error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0,
1542 	bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1543 	bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1546 	    m0->m_pkthdr.len, txq->cur, rate);
1549 	txq->queued++;
1550 	txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT;
1593 		if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) {
2248 	RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr);
2249 	RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr);
2250 	RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr);
2251 	RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr);
2405 		rt2661_reset_tx_ring(sc, &sc->txq[0]);
2406 		rt2661_reset_tx_ring(sc, &sc->txq[1]);
2407 		rt2661_reset_tx_ring(sc, &sc->txq[2]);
2408 		rt2661_reset_tx_ring(sc, &sc->txq[3]);