dev/iwi/if_iwi.c

342 		error = iwi_alloc_tx_ring(sc, &sc->txq[i], IWI_TX_RING_COUNT,
464 	iwi_free_tx_ring(sc, &sc->txq[0]);
465 	iwi_free_tx_ring(sc, &sc->txq[1]);
466 	iwi_free_tx_ring(sc, &sc->txq[2]);
467 	iwi_free_tx_ring(sc, &sc->txq[3]);
1611 iwi_tx_intr(struct iwi_softc *sc, struct iwi_tx_ring *txq)
1616 	hw = CSR_READ_4(sc, txq->csr_ridx);
1618 	while (txq->next != hw) {
1619 		data = &txq->data[txq->next];
1620 		DPRINTFN(15, ("tx done idx=%u\n", txq->next));
1621 		bus_dmamap_sync(txq->data_dmat, data->map,
1623 		bus_dmamap_unload(txq->data_dmat, data->map);
1627 		txq->queued--;
1628 		txq->next = (txq->next + 1) % IWI_TX_RING_COUNT;
1700 		iwi_tx_intr(sc, &sc->txq[0]);
1703 		iwi_tx_intr(sc, &sc->txq[1]);
1706 		iwi_tx_intr(sc, &sc->txq[2]);
1709 		iwi_tx_intr(sc, &sc->txq[3]);
1782 	struct iwi_tx_ring *txq = &sc->txq[ac];
1864 	data = &txq->data[txq->cur];
1865 	desc = &txq->desc[txq->cur];
1871 	error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs,
1889 		error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map,
1923 	bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1924 	bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1926 	DPRINTFN(5, ("sending data frame txq=%u idx=%u len=%u nseg=%u\n",
1927 	    ac, txq->cur, le16toh(desc->len), nsegs));
1929 	txq->queued++;
1930 	txq->cur = (txq->cur + 1) % IWI_TX_RING_COUNT;
1931 	CSR_WRITE_4(sc, txq->csr_widx, txq->cur);
1979 		if (sc->txq[ac].queued > IWI_TX_RING_COUNT - 8) {
3128 	CSR_WRITE_4(sc, IWI_CSR_TX1_BASE, sc->txq[0].physaddr);
3129 	CSR_WRITE_4(sc, IWI_CSR_TX1_SIZE, sc->txq[0].count);
3130 	CSR_WRITE_4(sc, IWI_CSR_TX1_WIDX, sc->txq[0].cur);
3132 	CSR_WRITE_4(sc, IWI_CSR_TX2_BASE, sc->txq[1].physaddr);
3133 	CSR_WRITE_4(sc, IWI_CSR_TX2_SIZE, sc->txq[1].count);
3134 	CSR_WRITE_4(sc, IWI_CSR_TX2_WIDX, sc->txq[1].cur);
3136 	CSR_WRITE_4(sc, IWI_CSR_TX3_BASE, sc->txq[2].physaddr);
3137 	CSR_WRITE_4(sc, IWI_CSR_TX3_SIZE, sc->txq[2].count);
3138 	CSR_WRITE_4(sc, IWI_CSR_TX3_WIDX, sc->txq[2].cur);
3140 	CSR_WRITE_4(sc, IWI_CSR_TX4_BASE, sc->txq[3].physaddr);
3141 	CSR_WRITE_4(sc, IWI_CSR_TX4_SIZE, sc->txq[3].count);
3142 	CSR_WRITE_4(sc, IWI_CSR_TX4_WIDX, sc->txq[3].cur);
3211 	iwi_reset_tx_ring(sc, &sc->txq[0]);
3212 	iwi_reset_tx_ring(sc, &sc->txq[1]);
3213 	iwi_reset_tx_ring(sc, &sc->txq[2]);
3214 	iwi_reset_tx_ring(sc, &sc->txq[3]);