Lines Matching defs:tmp
1122 uint32_t tmp;
1157 tmp = MEM_READ_4(sc, IWI_MEM_EEPROM_CTL);
1158 val |= ((tmp & IWI_EEPROM_Q) >> IWI_EEPROM_SHIFT_Q) << n;
2086 uint32_t tmp;
2101 tmp = CSR_READ_4(sc, IWI_CSR_RST);
2102 CSR_WRITE_4(sc, IWI_CSR_RST, tmp | IWI_RST_PRINCETON_RESET);
2110 uint32_t tmp;
2115 tmp = CSR_READ_4(sc, IWI_CSR_CTL);
2116 CSR_WRITE_4(sc, IWI_CSR_CTL, tmp | IWI_CTL_INIT);
2132 tmp = CSR_READ_4(sc, IWI_CSR_RST);
2133 CSR_WRITE_4(sc, IWI_CSR_RST, tmp | IWI_RST_SOFT_RESET);
2137 tmp = CSR_READ_4(sc, IWI_CSR_CTL);
2138 CSR_WRITE_4(sc, IWI_CSR_CTL, tmp | IWI_CTL_INIT);
2346 uint32_t tmp;
2370 tmp = CSR_READ_4(sc, IWI_CSR_RST);
2371 tmp &= ~IWI_RST_PRINCETON_RESET;
2372 CSR_WRITE_4(sc, IWI_CSR_RST, tmp);
2422 uint32_t sentinel, ctl, src, dst, sum, len, mlen, tmp;
2473 tmp = CSR_READ_4(sc, IWI_CSR_RST);
2474 tmp &= ~(IWI_RST_MASTER_DISABLED | IWI_RST_STOP_MASTER);
2475 CSR_WRITE_4(sc, IWI_CSR_RST, tmp);
2504 tmp = CSR_READ_4(sc, IWI_CSR_CTL);
2505 CSR_WRITE_4(sc, IWI_CSR_CTL, tmp | IWI_CTL_ALLOW_STANDBY);