Lines Matching refs:sc
327 #define CSR_READ_1(sc, reg) \
328 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
330 #define CSR_READ_2(sc, reg) \
331 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
333 #define CSR_READ_4(sc, reg) \
334 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
336 #define CSR_WRITE_1(sc, reg, val) \
337 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
339 #define CSR_WRITE_2(sc, reg, val) \
340 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
342 #define CSR_WRITE_4(sc, reg, val) \
343 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
345 #define CSR_WRITE_MULTI_1(sc, reg, buf, len) \
346 bus_space_write_multi_1((sc)->sc_st, (sc)->sc_sh, (reg), \
352 #define MEM_READ_1(sc, addr) \
353 (CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)), \
354 CSR_READ_1((sc), IPW_CSR_INDIRECT_DATA))
356 #define MEM_READ_4(sc, addr) \
357 (CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)), \
358 CSR_READ_4((sc), IPW_CSR_INDIRECT_DATA))
360 #define MEM_WRITE_1(sc, addr, val) do { \
361 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
362 CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \
365 #define MEM_WRITE_2(sc, addr, val) do { \
366 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
367 CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \
370 #define MEM_WRITE_4(sc, addr, val) do { \
371 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
372 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \
375 #define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \
376 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
377 CSR_WRITE_MULTI_1((sc), IPW_CSR_INDIRECT_DATA, (buf), (len)); \
383 #define IPW_EEPROM_CTL(sc, val) do { \
384 MEM_WRITE_4((sc), IPW_MEM_EEPROM_CTL, (val)); \