dev/pci/if_iwm.c

1074 iwm_write_prph_unlocked(struct iwm_softc *sc, uint32_t addr, uint32_t val)
1079 	IWM_WRITE(sc, IWM_HBUS_TARG_PRPH_WDAT, val);
1083 iwm_write_prph(struct iwm_softc *sc, uint32_t addr, uint32_t val)
1086 	iwm_write_prph_unlocked(sc, addr, val);
1090 iwm_write_prph64(struct iwm_softc *sc, uint64_t addr, uint64_t val)
1092 	iwm_write_prph(sc, (uint32_t)addr, val & 0xffffffff);
1093 	iwm_write_prph(sc, (uint32_t)addr + 4, val >> 32);
1123 			uint32_t val = vals ? vals[offs] : 0;
1124 			IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WDAT, val);
1134 iwm_write_mem32(struct iwm_softc *sc, uint32_t addr, uint32_t val)
1136 	return iwm_write_mem(sc, addr, &val, 1);
1204 	uint32_t val;
1207 		val = iwm_read_prph(sc, reg) & mask;
1208 		val |= bits;
1209 		iwm_write_prph(sc, reg, val);
2165 	uint32_t mask, val, reg_val = 0;
2192 	val = IWM_READ(sc, IWM_CSR_HW_IF_CONFIG_REG);
2193 	val &= ~mask;
2194 	val |= reg_val;
2195 	IWM_WRITE(sc, IWM_CSR_HW_IF_CONFIG_REG, val);
4214 	uint32_t val, last_read_idx = 0;
4255 			val = IWM_READ(sc, IWM_FH_UCODE_LOAD_STATUS);
4256 			val = val | (sec_num << shift_param);
4257 			IWM_WRITE(sc, IWM_FH_UCODE_LOAD_STATUS, val);
4632 	uint32_t val;
4634 	val = le32toh(phy_info->non_cfg_phy[IWM_RX_INFO_ENERGY_ANT_ABC_IDX]);
4635 	energy_a = (val & IWM_RX_INFO_ENERGY_ANT_A_MSK) >>
4638 	energy_b = (val & IWM_RX_INFO_ENERGY_ANT_B_MSK) >>
4641 	energy_c = (val & IWM_RX_INFO_ENERGY_ANT_C_MSK) >>
6565 	uint16_t val;
6573 	val = htole16(sta_id << 12 | len);
6579 	scd_bc_tbl[qid].tfd_offset[idx] = val;
6581 		scd_bc_tbl[qid].tfd_offset[IWM_TFD_QUEUE_SIZE_MAX + idx] = val;
6590 	uint16_t val;
6594 	val = htole16(1 | (sta_id << 12));
6600 	scd_bc_tbl[qid].tfd_offset[idx] = val;
6602 		scd_bc_tbl[qid].tfd_offset[IWM_TFD_QUEUE_SIZE_MAX + idx] = val;