dev/pci/if_iwm.c

1287 iwm_alloc_rx_ring(struct iwm_softc *sc, struct iwm_rx_ring *ring)
1293 	ring->cur = 0;
1305 	err = iwm_dma_contig_alloc(sc->sc_dmat, &ring->free_desc_dma, size, 256);
1307 		printf("%s: could not allocate RX ring DMA memory\n",
1311 	ring->desc = ring->free_desc_dma.vaddr;
1314 	err = iwm_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma,
1315 	    sizeof(*ring->stat), 16);
1321 	ring->stat = ring->stat_dma.vaddr;
1325 		err = iwm_dma_contig_alloc(sc->sc_dmat, &ring->used_desc_dma,
1328 			printf("%s: could not allocate RX ring DMA memory\n",
1335 		struct iwm_rx_data *data = &ring->data[i];
1353 fail:	iwm_free_rx_ring(sc, ring);
1385 iwm_reset_rx_ring(struct iwm_softc *sc, struct iwm_rx_ring *ring)
1387 	ring->cur = 0;
1388 	bus_dmamap_sync(sc->sc_dmat, ring->stat_dma.map, 0,
1389 	    ring->stat_dma.size, BUS_DMASYNC_PREWRITE);
1390 	memset(ring->stat, 0, sizeof(*ring->stat));
1391 	bus_dmamap_sync(sc->sc_dmat, ring->stat_dma.map, 0,
1392 	    ring->stat_dma.size, BUS_DMASYNC_POSTWRITE);
1397 iwm_free_rx_ring(struct iwm_softc *sc, struct iwm_rx_ring *ring)
1401 	iwm_dma_contig_free(&ring->free_desc_dma);
1402 	iwm_dma_contig_free(&ring->stat_dma);
1403 	iwm_dma_contig_free(&ring->used_desc_dma);
1411 		struct iwm_rx_data *data = &ring->data[i];
1426 iwm_alloc_tx_ring(struct iwm_softc *sc, struct iwm_tx_ring *ring, int qid)
1432 	ring->qid = qid;
1433 	ring->queued = 0;
1434 	ring->cur = 0;
1435 	ring->tail = 0;
1439 	err = iwm_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, size, 256);
1441 		printf("%s: could not allocate TX ring DMA memory\n",
1445 	ring->desc = ring->desc_dma.vaddr;
1470 	err = iwm_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, size, 4);
1475 	ring->cmd = ring->cmd_dma.vaddr;
1477 	paddr = ring->cmd_dma.paddr;
1479 		struct iwm_tx_data *data = &ring->data[i];
1502 	KASSERT(paddr == ring->cmd_dma.paddr + size);
1505 fail:	iwm_free_tx_ring(sc, ring);
1510 iwm_reset_tx_ring(struct iwm_softc *sc, struct iwm_tx_ring *ring)
1515 		struct iwm_tx_data *data = &ring->data[i];
1526 	memset(ring->desc, 0, ring->desc_dma.size);
1527 	bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0,
1528 	    ring->desc_dma.size, BUS_DMASYNC_PREWRITE);
1529 	sc->qfullmsk &= ~(1 << ring->qid);
1530 	sc->qenablemsk &= ~(1 << ring->qid);
1532 	if (ring->qid == sc->cmdqid && ring->queued > 0) {
1536 	ring->queued = 0;
1537 	ring->cur = 0;
1538 	ring->tail = 0;
1542 iwm_free_tx_ring(struct iwm_softc *sc, struct iwm_tx_ring *ring)
1546 	iwm_dma_contig_free(&ring->desc_dma);
1547 	iwm_dma_contig_free(&ring->cmd_dma);
1550 		struct iwm_tx_data *data = &ring->data[i];
2286 	/* Set physical address of RX ring (256-byte aligned). */
2337 		/* Set physical address of TX ring (256-byte aligned). */
2446 	struct iwm_tx_ring *ring = &sc->txq[qid];
2460 		!((ssn - ring->cur) & 0x3f) &&
2461 		(ssn != ring->cur);
2467 	ring->cur = idx;
2468 	ring->tail = idx;
3565 	struct iwm_tx_ring *ring;
3584 	ring = &sc->txq[qid];
3637 		if (ring->cur != IWM_AGG_SSN_TO_TXQ_IDX(ssn)) {
3639 			KASSERT(ring->cur == IWM_AGG_SSN_TO_TXQ_IDX(ssn));
3673 		iwm_txq_advance(sc, ring, ring->cur);
3674 		iwm_clear_oactive(sc, ring);
4567 	struct iwm_rx_ring *ring = &sc->rxq;
4568 	struct iwm_rx_data *data = &ring->data[idx];
4607 		((uint64_t *)ring->desc)[idx] =
4609 		bus_dmamap_sync(sc->sc_dmat, ring->free_desc_dma.map,
4613 		((uint32_t *)ring->desc)[idx] =
4615 		bus_dmamap_sync(sc->sc_dmat, ring->free_desc_dma.map,
5709 iwm_txq_advance(struct iwm_softc *sc, struct iwm_tx_ring *ring, int idx)
5713 	while (ring->tail != idx) {
5714 		txd = &ring->data[ring->tail];
5716 			iwm_reset_sched(sc, ring->qid, ring->tail, IWM_STATION_ID);
5718 			ring->queued--;
5720 		ring->tail = (ring->tail + 1) % IWM_TX_RING_COUNT;
5723 	wakeup(ring);
5856 	struct iwm_tx_ring *ring = &sc->txq[qid];
5878 	txd = &ring->data[idx];
5887 		iwm_ampdu_tx_done(sc, cmd_hdr, txd->in, ring,
5896 		iwm_txq_advance(sc, ring, IWM_AGG_SSN_TO_TXQ_IDX(ssn));
5897 		iwm_clear_oactive(sc, ring);
5902 iwm_clear_oactive(struct iwm_softc *sc, struct iwm_tx_ring *ring)
5907 	if (ring->queued < IWM_TX_RING_LOMARK) {
5908 		sc->qfullmsk &= ~(1 << ring->qid);
5969 	struct iwm_tx_ring *ring;
5997 	ring = &sc->txq[qid];
6022 		iwm_ampdu_rate_control(sc, ni, ring, ban->tid,
6031 	iwm_txq_advance(sc, ring, IWM_AGG_SSN_TO_TXQ_IDX(ssn));
6032 	iwm_clear_oactive(sc, ring);
6287 	struct iwm_tx_ring *ring = &sc->txq[sc->cmdqid];
6302 	idx = ring->cur;
6329 	desc = &ring->desc[idx];
6330 	txdata = &ring->data[idx];
6369 		cmd = &ring->cmd[idx];
6376 		cmd->hdr_wide.qid = ring->qid;
6384 		cmd->hdr.qid = ring->qid;
6408 		bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map,
6409 		    (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr,
6412 	bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map,
6413 	    (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr,
6422 		if (ring->queued == 0 && !iwm_nic_lock(sc)) {
6428 	iwm_update_sched(sc, ring->qid, ring->cur, 0, 0);
6430 	/* Kick command ring. */
6431 	ring->queued++;
6432 	ring->cur = (ring->cur + 1) % IWM_TX_RING_COUNT;
6433 	IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
6529 	struct iwm_tx_ring *ring = &sc->txq[sc->cmdqid];
6536 	data = &ring->data[idx];
6545 	wakeup(&ring->desc[idx]);
6547 	if (ring->queued == 0) {
6550 	} else if (--ring->queued == 0) {
6719 	struct iwm_tx_ring *ring;
6786 	ring = &sc->txq[qid];
6787 	desc = &ring->desc[ring->cur];
6789 	data = &ring->data[ring->cur];
6791 	cmd = &ring->cmd[ring->cur];
6794 	cmd->hdr.qid = ring->qid;
6795 	cmd->hdr.idx = ring->cur;
7003 	bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map,
7004 	    (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr,
7006 	bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map,
7007 	    (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr,
7010 	iwm_update_sched(sc, ring->qid, ring->cur, tx->sta_id, totlen);
7012 	/* Kick TX ring. */
7013 	ring->cur = (ring->cur + 1) % IWM_TX_RING_COUNT;
7014 	IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
7016 	/* Mark TX ring as full if we reach a certain threshold. */
7017 	if (++ring->queued > IWM_TX_RING_HIMARK) {
7018 		sc->qfullmsk |= 1 << ring->qid;
7022 		sc->sc_tx_timer[ring->qid] = 15;
7051 		struct iwm_tx_ring *ring = &sc->txq[i];
7056 		while (ring->queued > 0) {
7057 			err = tsleep_nsec(ring, 0, "iwmflush",
10946 		struct iwm_tx_ring *ring = &sc->txq[i];
10947 		printf("  tx ring %2d: qid=%-2d cur=%-3d "
10949 		    i, ring->qid, ring->cur, ring->queued);
10951 	printf("  rx ring: cur=%d\n", sc->rxq.cur);
11014 			/* Take mbuf m0 off the RX ring. */
11322 			    "rx ring %d[%d]\n",
12014 			printf("%s: could not allocate TX ring %d\n",
12022 		printf("%s: could not allocate RX ring\n", DEVNAME(sc));