Lines Matching defs:reg
1140 iwm_poll_bit(struct iwm_softc *sc, int reg, uint32_t bits, uint32_t mask,
1144 if ((IWM_READ(sc, reg) & mask) == (bits & mask)) {
1201 iwm_set_bits_mask_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits,
1207 val = iwm_read_prph(sc, reg) & mask;
1209 iwm_write_prph(sc, reg, val);
1217 iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)
1219 return iwm_set_bits_mask_prph(sc, reg, bits, ~0);
1223 iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)
1225 return iwm_set_bits_mask_prph(sc, reg, 0, ~bits);
10812 printf("%s: 0x%08X | isr status reg\n", DEVNAME(sc),
11739 pcireg_t reg, memtype;
11776 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40);
11777 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00);
11799 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
11801 if (reg & PCI_COMMAND_INTERRUPT_DISABLE)
11802 reg &= ~PCI_COMMAND_INTERRUPT_DISABLE;
11804 PCI_COMMAND_STATUS_REG, reg);
12211 pcireg_t reg;
12217 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40);
12218 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00);
12222 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
12224 if (reg & PCI_COMMAND_INTERRUPT_DISABLE)
12225 reg &= ~PCI_COMMAND_INTERRUPT_DISABLE;
12227 PCI_COMMAND_STATUS_REG, reg);