Lines Matching refs:sc
184 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int);
189 static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq,
262 ath_legacy_attach_comp_func(struct ath_softc *sc)
270 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) {
272 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc);
275 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc);
278 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc);
300 _ath_power_setpower(struct ath_softc *sc, int power_state, int selfgen,
303 ATH_LOCK_ASSERT(sc);
305 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d, target=%d, cur=%d\n",
310 sc->sc_powersave_refcnt,
311 sc->sc_target_powerstate,
312 sc->sc_cur_powerstate);
314 sc->sc_target_powerstate = power_state;
323 if ((sc->sc_powersave_refcnt == 0 || power_state == HAL_PM_AWAKE) &&
324 power_state != sc->sc_cur_powerstate) {
325 sc->sc_cur_powerstate = power_state;
326 ath_hal_setpower(sc->sc_ah, power_state);
337 sc->sc_cur_powerstate == HAL_PM_AWAKE &&
338 sc->sc_target_selfgen_state != HAL_PM_AWAKE) {
339 ath_hal_setselfgenpower(sc->sc_ah,
340 sc->sc_target_selfgen_state);
354 _ath_power_set_selfgen(struct ath_softc *sc, int power_state, const char *file, int line)
357 ATH_LOCK_ASSERT(sc);
359 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d\n",
364 sc->sc_target_selfgen_state);
366 sc->sc_target_selfgen_state = power_state;
375 if (sc->sc_cur_powerstate == HAL_PM_AWAKE) {
376 ath_hal_setselfgenpower(sc->sc_ah, power_state);
390 _ath_power_set_power_state(struct ath_softc *sc, int power_state, const char *file, int line)
392 ATH_LOCK_ASSERT(sc);
394 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d\n",
399 sc->sc_powersave_refcnt);
401 sc->sc_powersave_refcnt++;
407 if (power_state != sc->sc_cur_powerstate) {
408 ath_hal_setpower(sc->sc_ah, power_state);
409 sc->sc_cur_powerstate = power_state;
413 if (sc->sc_cur_powerstate == HAL_PM_AWAKE &&
414 sc->sc_target_selfgen_state != HAL_PM_AWAKE) {
415 ath_hal_setselfgenpower(sc->sc_ah,
416 sc->sc_target_selfgen_state);
428 _ath_power_restore_power_state(struct ath_softc *sc, const char *file, int line)
431 ATH_LOCK_ASSERT(sc);
433 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) refcnt=%d, target state=%d\n",
437 sc->sc_powersave_refcnt,
438 sc->sc_target_powerstate);
440 if (sc->sc_powersave_refcnt == 0)
441 device_printf(sc->sc_dev, "%s: refcnt=0?\n", __func__);
443 sc->sc_powersave_refcnt--;
445 if (sc->sc_powersave_refcnt == 0 &&
446 sc->sc_target_powerstate != sc->sc_cur_powerstate) {
447 sc->sc_cur_powerstate = sc->sc_target_powerstate;
448 ath_hal_setpower(sc->sc_ah, sc->sc_target_powerstate);
454 if (sc->sc_cur_powerstate == HAL_PM_AWAKE &&
455 sc->sc_target_selfgen_state != HAL_PM_AWAKE) {
456 ath_hal_setselfgenpower(sc->sc_ah,
457 sc->sc_target_selfgen_state);
474 ath_setup_hal_config(struct ath_softc *sc, HAL_OPS_CONFIG *ah_config)
478 if (sc->sc_pci_devinfo & (ATH_PCI_CUS198 | ATH_PCI_CUS230)) {
485 device_printf(sc->sc_dev, "configuring for %s\n",
486 (sc->sc_pci_devinfo & ATH_PCI_CUS198) ?
490 if (sc->sc_pci_devinfo & ATH_PCI_CUS217)
491 device_printf(sc->sc_dev, "CUS217 card detected\n");
493 if (sc->sc_pci_devinfo & ATH_PCI_CUS252)
494 device_printf(sc->sc_dev, "CUS252 card detected\n");
496 if (sc->sc_pci_devinfo & ATH_PCI_AR9565_1ANT)
497 device_printf(sc->sc_dev, "WB335 1-ANT card detected\n");
499 if (sc->sc_pci_devinfo & ATH_PCI_AR9565_2ANT)
500 device_printf(sc->sc_dev, "WB335 2-ANT card detected\n");
502 if (sc->sc_pci_devinfo & ATH_PCI_BT_ANT_DIV)
503 device_printf(sc->sc_dev,
506 if (sc->sc_pci_devinfo & ATH_PCI_KILLER)
507 device_printf(sc->sc_dev, "Killer Wireless card detected\n");
516 if (sc->sc_pci_devinfo & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
517 if (!(sc->sc_pci_devinfo & ATH9K_PCI_BT_ANT_DIV))
521 if (sc->sc_pci_devinfo & ATH9K_PCI_BT_ANT_DIV) {
523 device_printf(sc->sc_dev, "Set BT/WLAN RX diversity capability\n");
527 if (sc->sc_pci_devinfo & ATH_PCI_D3_L1_WAR) {
529 device_printf(sc->sc_dev, "Enable WAR for ASPM D3/L1\n");
533 if (sc->sc_pci_devinfo & ATH9K_PCI_NO_PLL_PWRSAVE) {
535 device_printf(sc->sc_dev, "Disable PLL PowerSave\n");
547 ath_fetch_mac_kenv(struct ath_softc *sc, uint8_t *macaddr)
561 device_get_name(sc->sc_dev),
562 device_get_unit(sc->sc_dev));
571 device_printf(sc->sc_dev,
602 ath_attach(u_int16_t devid, struct ath_softc *sc)
604 struct ieee80211com *ic = &sc->sc_ic;
612 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid);
614 ic->ic_softc = sc;
615 ic->ic_name = device_get_nameunit(sc->sc_dev);
624 ath_setup_hal_config(sc, &ah_config);
626 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh,
627 sc->sc_eepromdata, &ah_config, &status);
629 device_printf(sc->sc_dev,
634 sc->sc_ah = ah;
635 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */
637 sc->sc_debug = ath_debug;
647 ATH_LOCK(sc);
648 ath_power_setpower(sc, HAL_PM_AWAKE, 1);
649 ATH_UNLOCK(sc);
657 if (ath_hal_hasedma(sc->sc_ah)) {
658 sc->sc_isedma = 1;
659 ath_recv_setup_edma(sc);
660 ath_xmit_setup_edma(sc);
662 ath_recv_setup_legacy(sc);
663 ath_xmit_setup_legacy(sc);
666 if (ath_hal_hasmybeacon(sc->sc_ah)) {
667 sc->sc_do_mybeacon = 1;
677 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0);
685 sc->sc_needmib = 1;
690 sc->sc_keymax = ath_hal_keycachesize(ah);
691 if (sc->sc_keymax > ATH_KEYMAX) {
692 device_printf(sc->sc_dev,
694 ATH_KEYMAX, sc->sc_keymax);
695 sc->sc_keymax = ATH_KEYMAX;
701 for (i = 0; i < sc->sc_keymax; i++)
707 error = ath_getchannels(sc);
714 ath_rate_setup(sc, IEEE80211_MODE_11A);
715 ath_rate_setup(sc, IEEE80211_MODE_11B);
716 ath_rate_setup(sc, IEEE80211_MODE_11G);
717 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A);
718 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G);
719 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A);
720 ath_rate_setup(sc, IEEE80211_MODE_11NA);
721 ath_rate_setup(sc, IEEE80211_MODE_11NG);
722 ath_rate_setup(sc, IEEE80211_MODE_HALF);
723 ath_rate_setup(sc, IEEE80211_MODE_QUARTER);
726 ath_setcurmode(sc, IEEE80211_MODE_11A);
731 error = ath_desc_alloc(sc);
733 device_printf(sc->sc_dev,
737 error = ath_txdma_setup(sc);
739 device_printf(sc->sc_dev,
747 error = ath_rxdma_setup(sc);
749 device_printf(sc->sc_dev,
754 callout_init_mtx(&sc->sc_cal_ch, &sc->sc_mtx, 0);
755 callout_init_mtx(&sc->sc_wd_ch, &sc->sc_mtx, 0);
757 ATH_TXBUF_LOCK_INIT(sc);
759 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT,
760 taskqueue_thread_enqueue, &sc->sc_tq);
761 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq",
762 device_get_nameunit(sc->sc_dev));
764 TASK_INIT(&sc->sc_rxtask, 0, sc->sc_rx.recv_tasklet, sc);
765 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc);
766 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc);
767 TASK_INIT(&sc->sc_resettask,0, ath_reset_proc, sc);
768 TASK_INIT(&sc->sc_txqtask, 0, ath_txq_sched_tasklet, sc);
769 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc);
779 sc->sc_bhalq = ath_beaconq_setup(sc);
780 if (sc->sc_bhalq == (u_int) -1) {
781 device_printf(sc->sc_dev,
786 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
787 if (sc->sc_cabq == NULL) {
788 device_printf(sc->sc_dev, "unable to setup CAB xmit queue!\n");
793 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) {
794 device_printf(sc->sc_dev,
800 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) ||
801 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) ||
802 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) {
810 if (sc->sc_ac2q[WME_AC_VI] != NULL)
811 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]);
812 if (sc->sc_ac2q[WME_AC_BE] != NULL)
813 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]);
814 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK];
815 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK];
816 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK];
825 sc->sc_tx.xmit_attach_comp_func(sc);
833 sc->sc_setdefantenna = ath_setdefantenna;
834 sc->sc_rc = ath_rate_attach(sc);
835 if (sc->sc_rc == NULL) {
841 if (! ath_dfs_attach(sc)) {
842 device_printf(sc->sc_dev,
849 if (ath_spectral_attach(sc) < 0) {
850 device_printf(sc->sc_dev,
857 if (ath_btcoex_attach(sc) < 0) {
858 device_printf(sc->sc_dev,
865 if (ath_lna_div_attach(sc) < 0) {
866 device_printf(sc->sc_dev,
873 TASK_INIT(&sc->sc_dfstask, 0, ath_dfs_tasklet, sc);
876 sc->sc_blinking = 0;
877 sc->sc_ledstate = 1;
878 sc->sc_ledon = 0; /* low true */
879 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */
880 callout_init(&sc->sc_ledtimer, 1);
893 sc->sc_hardled = (1 == 0);
894 sc->sc_led_net_pin = -1;
895 sc->sc_led_pwr_pin = -1;
901 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID);
902 ath_led_config(sc);
955 sc->sc_splitmic = 1;
962 sc->sc_wmetkipmic = 1;
964 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR);
968 if (ath_hal_hasmcastkeysearch(sc->sc_ah) &&
969 !ath_hal_getmcastkeysearch(sc->sc_ah)) {
970 ath_hal_setmcastkeysearch(sc->sc_ah, 1);
972 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah);
979 setbit(sc->sc_keymap, i);
980 setbit(sc->sc_keymap, i+64);
981 if (sc->sc_splitmic) {
982 setbit(sc->sc_keymap, i+32);
983 setbit(sc->sc_keymap, i+32+64);
999 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK])
1006 sc->sc_hasbmask = ath_hal_hasbssidmask(ah);
1007 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah);
1008 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah);
1009 sc->sc_rxslink = ath_hal_self_linked_final_rxdesc(ah);
1014 sc->sc_rxtsf32 = 1;
1017 device_printf(sc->sc_dev, "RX timestamp: %d bits\n", i);
1021 device_printf(sc->sc_dev, "TX timestamp: %d bits\n", i);
1024 sc->sc_hasenforcetxop = ath_hal_hasenforcetxop(ah);
1025 sc->sc_rx_lnamixer = ath_hal_hasrxlnamixer(ah);
1026 sc->sc_hasdivcomb = ath_hal_hasdivantcomb(ah);
1043 if (sc->sc_pci_devinfo & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
1044 device_printf(sc->sc_dev, "%s: WB335: disabling LNA mixer diversity\n",
1046 sc->sc_dolnadiv = 0;
1067 sc->sc_txq_data_minfree = 10;
1077 sc->sc_txq_mcastq_maxdepth = MIN(64, ath_txbuf / 4);
1082 sc->sc_txq_node_psq_maxdepth = 16;
1088 sc->sc_txq_node_maxdepth = MIN(64, ath_txbuf / 4);
1091 sc->sc_cabq_enable = 1;
1101 if (resource_int_value(device_get_name(sc->sc_dev),
1102 device_get_unit(sc->sc_dev), "rx_chainmask",
1104 device_printf(sc->sc_dev, "Setting RX chainmask to 0x%x\n",
1106 (void) ath_hal_setrxchainmask(sc->sc_ah, rx_chainmask);
1108 if (resource_int_value(device_get_name(sc->sc_dev),
1109 device_get_unit(sc->sc_dev), "tx_chainmask",
1111 device_printf(sc->sc_dev, "Setting TX chainmask to 0x%x\n",
1113 (void) ath_hal_settxchainmask(sc->sc_ah, tx_chainmask);
1121 ath_hal_getrxchainmask(ah, &sc->sc_rxchainmask);
1122 ath_hal_gettxchainmask(ah, &sc->sc_txchainmask);
1128 sc->sc_mrrprot = 0; /* XXX should be a capability */
1134 &sc->sc_ent_cfg) == HAL_OK)
1135 sc->sc_use_ent = 1;
1146 device_printf(sc->sc_dev, "[HT] enabling HT modes\n");
1148 sc->sc_mrrprot = 1; /* XXX should be a capability */
1165 device_printf(sc->sc_dev,
1193 sc->sc_rx_stbc = 1;
1194 device_printf(sc->sc_dev,
1200 sc->sc_tx_stbc = 1;
1201 device_printf(sc->sc_dev,
1207 &sc->sc_rts_aggr_limit);
1208 if (sc->sc_rts_aggr_limit != (64 * 1024))
1209 device_printf(sc->sc_dev,
1211 sc->sc_rts_aggr_limit / 1024);
1218 sc->sc_has_ldpc = 1;
1219 device_printf(sc->sc_dev,
1225 device_printf(sc->sc_dev,
1233 sc->sc_hwq_limit_aggr = ATH_AGGR_MIN_QDEPTH;
1234 sc->sc_hwq_limit_nonaggr = ATH_NONAGGR_MIN_QDEPTH;
1235 sc->sc_tid_hwq_lo = ATH_AGGR_SCHED_LOW;
1236 sc->sc_tid_hwq_hi = ATH_AGGR_SCHED_HIGH;
1237 sc->sc_aggr_limit = ATH_AGGR_MAXSIZE;
1238 sc->sc_delim_min_pad = 0;
1247 sc->sc_ah->ah_config.ah_serialise_reg_war = 1;
1248 device_printf(sc->sc_dev,
1255 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP]);
1256 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP]);
1267 sc->sc_defant = ath_hal_getdefantenna(ah);
1273 sc->sc_hasveol = ath_hal_hasveol(ah);
1276 if (ath_fetch_mac_kenv(sc, ic->ic_macaddr) == 0) {
1283 if (sc->sc_hasbmask)
1284 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask);
1287 ic->ic_max_keyix = sc->sc_keymax;
1292 sc->sc_opmode = HAL_M_STA;
1307 sc->sc_node_free = ic->ic_node_free;
1309 sc->sc_node_cleanup = ic->ic_node_cleanup;
1317 sc->sc_addba_request = ic->ic_addba_request;
1318 sc->sc_addba_response = ic->ic_addba_response;
1319 sc->sc_addba_stop = ic->ic_addba_stop;
1320 sc->sc_bar_response = ic->ic_bar_response;
1321 sc->sc_addba_response_timeout = ic->ic_addba_response_timeout;
1339 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 0,
1341 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 1,
1348 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
1350 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
1358 if_ath_alq_init(&sc->sc_alq, device_get_nameunit(sc->sc_dev));
1359 if_ath_alq_setcfg(&sc->sc_alq,
1360 sc->sc_ah->ah_macVersion,
1361 sc->sc_ah->ah_macRev,
1362 sc->sc_ah->ah_phyRev,
1363 sc->sc_ah->ah_magic);
1370 ath_sysctlattach(sc);
1371 ath_sysctl_stats_attach(sc);
1372 ath_sysctl_hal_attach(sc);
1376 ath_announce(sc);
1381 ATH_LOCK(sc);
1382 ath_power_setpower(sc, HAL_PM_FULL_SLEEP, 1);
1383 ATH_UNLOCK(sc);
1387 ath_tx_cleanup(sc);
1388 ath_desc_free(sc);
1389 ath_txdma_teardown(sc);
1390 ath_rxdma_teardown(sc);
1395 sc->sc_invalid = 1;
1400 ath_detach(struct ath_softc *sc)
1423 ATH_LOCK(sc);
1424 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1425 ath_power_setpower(sc, HAL_PM_AWAKE, 1);
1430 ath_stop(sc);
1431 ATH_UNLOCK(sc);
1433 ieee80211_ifdetach(&sc->sc_ic);
1434 taskqueue_free(sc->sc_tq);
1436 if (sc->sc_tx99 != NULL)
1437 sc->sc_tx99->detach(sc->sc_tx99);
1439 ath_rate_detach(sc->sc_rc);
1441 if_ath_alq_tidyup(&sc->sc_alq);
1443 ath_lna_div_detach(sc);
1444 ath_btcoex_detach(sc);
1445 ath_spectral_detach(sc);
1446 ath_dfs_detach(sc);
1447 ath_desc_free(sc);
1448 ath_txdma_teardown(sc);
1449 ath_rxdma_teardown(sc);
1450 ath_tx_cleanup(sc);
1451 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */
1463 assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone)
1467 if (clone && sc->sc_hasbmask) {
1470 if ((sc->sc_bssidmask & (1<<i)) == 0)
1476 sc->sc_bssidmask |= 1<<i;
1477 sc->sc_hwbssidmask[0] &= ~mac[0];
1479 sc->sc_nbssid0++;
1483 reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN])
1488 if (i != 0 || --sc->sc_nbssid0 == 0) {
1489 sc->sc_bssidmask &= ~(1<<i);
1493 if (sc->sc_bssidmask & (1<<i))
1495 sc->sc_hwbssidmask[0] |= mask;
1506 assign_bslot(struct ath_softc *sc)
1512 if (sc->sc_bslot[slot] == NULL) {
1513 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL &&
1514 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL)
1528 struct ath_softc *sc = ic->ic_softc;
1539 ATH_LOCK(sc);
1543 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */
1544 device_printf(sc->sc_dev, "only 1 sta vap supported\n");
1547 if (sc->sc_nvaps) {
1562 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */
1563 device_printf(sc->sc_dev,
1572 if (sc->sc_nvaps != 0) {
1573 device_printf(sc->sc_dev,
1583 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) {
1598 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) {
1599 device_printf(sc->sc_dev,
1609 if (sc->sc_nvaps == 0)
1615 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode);
1621 if (needbeacon & TAILQ_EMPTY(&sc->sc_bbuf)) {
1622 device_printf(sc->sc_dev, "no beacon buffer available\n");
1628 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID);
1629 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1634 ATH_UNLOCK(sc);
1636 ATH_LOCK(sc);
1638 device_printf(sc->sc_dev, "%s: error %d creating vap\n",
1692 avp->av_bcbuf = TAILQ_FIRST(&sc->sc_bbuf);
1693 TAILQ_REMOVE(&sc->sc_bbuf, avp->av_bcbuf, bf_list);
1694 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) {
1699 avp->av_bslot = assign_bslot(sc);
1700 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL,
1702 sc->sc_bslot[avp->av_bslot] = vap;
1703 sc->sc_nbcnvaps++;
1705 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) {
1711 sc->sc_stagbeacons = 1;
1713 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ);
1718 sc->sc_nvaps++;
1720 sc->sc_nstavaps++;
1722 sc->sc_nmeshvaps++;
1726 sc->sc_opmode = HAL_M_IBSS;
1729 sc->sc_opmode = HAL_M_STA;
1734 sc->sc_tdma = 1;
1736 sc->sc_stagbeacons = 0;
1746 sc->sc_opmode = HAL_M_HOSTAP;
1749 sc->sc_opmode = HAL_M_MONITOR;
1755 if (sc->sc_hastsfadd) {
1759 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons);
1765 sc->sc_swbmiss = 1;
1767 ATH_UNLOCK(sc);
1774 reclaim_address(sc, mac);
1775 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1778 ATH_UNLOCK(sc);
1786 struct ath_softc *sc = ic->ic_softc;
1787 struct ath_hal *ah = sc->sc_ah;
1790 ATH_LOCK(sc);
1791 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1792 ATH_UNLOCK(sc);
1794 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
1795 if (sc->sc_running) {
1803 ath_stoprecv(sc, 1); /* stop recv side */
1804 ath_rx_flush(sc);
1805 ath_draintxq(sc, ATH_RESET_DEFAULT); /* stop hw xmit side */
1829 ath_draintxq(sc, ATH_RESET_DEFAULT);
1831 ATH_LOCK(sc);
1839 sc->sc_bslot[avp->av_bslot] = NULL;
1840 sc->sc_nbcnvaps--;
1842 ath_beacon_return(sc, avp->av_bcbuf);
1844 if (sc->sc_nbcnvaps == 0) {
1845 sc->sc_stagbeacons = 0;
1846 if (sc->sc_hastsfadd)
1847 ath_hal_settsfadjust(sc->sc_ah, 0);
1852 ath_tx_draintxq(sc, &avp->av_mcastq);
1858 sc->sc_nstavaps--;
1859 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss)
1860 sc->sc_swbmiss = 0;
1864 reclaim_address(sc, vap->iv_myaddr);
1865 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask);
1867 sc->sc_nmeshvaps--;
1870 sc->sc_nvaps--;
1873 if (sc->sc_tdma && sc->sc_nvaps == 0) {
1874 sc->sc_tdma = 0;
1875 sc->sc_swbmiss = 0;
1880 if (sc->sc_running) {
1885 if (ath_startrecv(sc) != 0)
1886 device_printf(sc->sc_dev,
1888 if (sc->sc_beacons) { /* restart beacons */
1890 if (sc->sc_tdma)
1891 ath_tdma_config(sc, NULL);
1894 ath_beacon_config(sc, NULL);
1896 ath_hal_intrset(ah, sc->sc_imask);
1900 ath_power_restore_power_state(sc);
1901 ATH_UNLOCK(sc);
1905 ath_suspend(struct ath_softc *sc)
1907 struct ieee80211com *ic = &sc->sc_ic;
1909 sc->sc_resume_up = ic->ic_nrunning != 0;
1926 ath_hal_intrset(sc->sc_ah, 0);
1927 taskqueue_block(sc->sc_tq);
1929 ATH_LOCK(sc);
1930 callout_stop(&sc->sc_cal_ch);
1931 ATH_UNLOCK(sc);
1938 ath_hal_enablepcie(sc->sc_ah, 1, 1);
1948 ath_reset_keycache(struct ath_softc *sc)
1950 struct ieee80211com *ic = &sc->sc_ic;
1951 struct ath_hal *ah = sc->sc_ah;
1954 ATH_LOCK(sc);
1955 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1956 for (i = 0; i < sc->sc_keymax; i++)
1958 ath_power_restore_power_state(sc);
1959 ATH_UNLOCK(sc);
1968 ath_update_chainmasks(struct ath_softc *sc, struct ieee80211_channel *chan)
1975 sc->sc_cur_rxchainmask = sc->sc_rxchainmask;
1977 sc->sc_cur_txchainmask = sc->sc_txchainmask;
1979 sc->sc_cur_txchainmask = 1;
1982 DPRINTF(sc, ATH_DEBUG_RESET,
1985 sc->sc_cur_txchainmask,
1986 sc->sc_cur_rxchainmask);
1990 ath_resume(struct ath_softc *sc)
1992 struct ieee80211com *ic = &sc->sc_ic;
1993 struct ath_hal *ah = sc->sc_ah;
2002 ath_update_chainmasks(sc,
2003 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan);
2004 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
2005 sc->sc_cur_rxchainmask);
2008 ATH_LOCK(sc);
2009 ath_power_setselfgen(sc, HAL_PM_AWAKE);
2010 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2011 ath_power_setpower(sc, HAL_PM_AWAKE, 1);
2012 ATH_UNLOCK(sc);
2014 ath_hal_reset(ah, sc->sc_opmode,
2015 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan,
2017 ath_reset_keycache(sc);
2019 ATH_RX_LOCK(sc);
2020 sc->sc_rx_stopped = 1;
2021 sc->sc_rx_resetted = 1;
2022 ATH_RX_UNLOCK(sc);
2025 ath_dfs_radar_enable(sc, ic->ic_curchan);
2028 ath_spectral_enable(sc, ic->ic_curchan);
2033 ath_btcoex_enable(sc, ic->ic_curchan);
2039 if (sc->sc_hasenforcetxop && sc->sc_tdma)
2040 ath_hal_setenforcetxop(sc->sc_ah, 1);
2042 ath_hal_setenforcetxop(sc->sc_ah, 0);
2045 ath_led_config(sc);
2048 if (sc->sc_resume_up)
2051 ATH_LOCK(sc);
2052 ath_power_restore_power_state(sc);
2053 ATH_UNLOCK(sc);
2059 ath_shutdown(struct ath_softc *sc)
2062 ATH_LOCK(sc);
2063 ath_stop(sc);
2064 ATH_UNLOCK(sc);
2074 struct ath_softc *sc = arg;
2075 struct ath_hal *ah = sc->sc_ah;
2083 ATH_PCU_LOCK(sc);
2084 if (sc->sc_inreset_cnt) {
2088 DPRINTF(sc, ATH_DEBUG_ANY,
2091 ATH_PCU_UNLOCK(sc);
2096 if (sc->sc_invalid) {
2101 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__);
2102 ATH_PCU_UNLOCK(sc);
2106 ATH_PCU_UNLOCK(sc);
2111 ATH_LOCK(sc);
2112 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2113 ATH_UNLOCK(sc);
2115 if (sc->sc_ic.ic_nrunning == 0 && sc->sc_running == 0) {
2118 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_nrunning %d sc_running %d\n",
2119 __func__, sc->sc_ic.ic_nrunning, sc->sc_running);
2122 ATH_PCU_UNLOCK(sc);
2124 ATH_LOCK(sc);
2125 ath_power_restore_power_state(sc);
2126 ATH_UNLOCK(sc);
2137 status = atomic_get((int32 *)&sc->sc_intr_status);
2141 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
2142 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1, "ath_intr: mask=0x%.8x", status);
2144 if_ath_alq_post_intr(&sc->sc_alq, status, ah->ah_intrstate,
2148 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 5,
2162 sc->sc_intr_stats.sync_intr[i]++;
2165 status &= sc->sc_imask; /* discard unasked for bits */
2169 ATH_PCU_UNLOCK(sc);
2171 ATH_LOCK(sc);
2172 ath_power_restore_power_state(sc);
2173 ATH_UNLOCK(sc);
2182 sc->sc_intr_cnt++;
2183 ATH_PCU_UNLOCK(sc);
2191 sc->sc_stats.ast_hardware++;
2193 taskqueue_enqueue(sc->sc_tq, &sc->sc_fataltask);
2203 if (sc->sc_tdma) {
2204 if (sc->sc_tdmaswba == 0) {
2205 struct ieee80211com *ic = &sc->sc_ic;
2208 ath_tdma_beacon_send(sc, vap);
2209 sc->sc_tdmaswba =
2212 sc->sc_tdmaswba--;
2216 ath_beacon_proc(sc, 0);
2223 sc->sc_rx.recv_sched(sc, 1);
2229 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXEOL");
2230 if (! sc->sc_isedma) {
2231 ATH_PCU_LOCK(sc);
2237 sc->sc_stats.ast_rxeol++;
2247 imask = sc->sc_imask;
2261 if (! sc->sc_kickpcu)
2262 sc->sc_rxlink = NULL;
2263 sc->sc_kickpcu = 1;
2264 ATH_PCU_UNLOCK(sc);
2271 sc->sc_rx.recv_sched(sc, 1);
2274 sc->sc_stats.ast_txurn++;
2283 sc->sc_stats.ast_rx_intr++;
2284 sc->sc_rx.recv_sched(sc, 1);
2287 sc->sc_stats.ast_tx_intr++;
2293 if (! sc->sc_isedma) {
2294 ATH_PCU_LOCK(sc);
2296 ath_hal_gettxintrtxqs(sc->sc_ah, &txqs);
2297 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 3,
2300 sc->sc_txq_active,
2301 sc->sc_txq_active | txqs);
2302 sc->sc_txq_active |= txqs;
2303 ATH_PCU_UNLOCK(sc);
2305 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask);
2308 sc->sc_stats.ast_bmiss++;
2309 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask);
2312 sc->sc_stats.ast_tx_timeout++;
2314 sc->sc_stats.ast_tx_cst++;
2316 sc->sc_stats.ast_mib++;
2317 ATH_PCU_LOCK(sc);
2327 ath_hal_mibevent(ah, &sc->sc_halstats);
2334 if (sc->sc_kickpcu == 0)
2335 ath_hal_intrset(ah, sc->sc_imask);
2336 ATH_PCU_UNLOCK(sc);
2340 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXORN");
2341 sc->sc_stats.ast_rxorn++;
2346 device_printf(sc->sc_dev, "%s: TSFOOR\n", __func__);
2347 sc->sc_syncbeacon = 1;
2348 ATH_LOCK(sc);
2349 ath_power_setpower(sc, HAL_PM_AWAKE, 0);
2350 ATH_UNLOCK(sc);
2353 ath_btcoex_mci_intr(sc);
2356 ATH_PCU_LOCK(sc);
2357 sc->sc_intr_cnt--;
2358 ATH_PCU_UNLOCK(sc);
2360 ATH_LOCK(sc);
2361 ath_power_restore_power_state(sc);
2362 ATH_UNLOCK(sc);
2368 struct ath_softc *sc = arg;
2373 if (sc->sc_invalid)
2376 device_printf(sc->sc_dev, "hardware error; resetting\n");
2382 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) {
2385 device_printf(sc->sc_dev,
2389 ath_reset(sc, ATH_RESET_NOLOSS, HAL_RESET_FORCE_COLD);
2395 struct ath_softc *sc = vap->iv_ic->ic_softc;
2411 ATH_LOCK(sc);
2412 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2413 ATH_UNLOCK(sc);
2416 u_int64_t lastrx = sc->sc_lastrx;
2417 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah);
2422 DPRINTF(sc, ATH_DEBUG_BEACON,
2429 sc->sc_stats.ast_bmiss_phantom++;
2431 ATH_LOCK(sc);
2432 ath_power_restore_power_state(sc);
2433 ATH_UNLOCK(sc);
2450 ATH_LOCK(sc);
2451 ath_power_setpower(sc, HAL_PM_AWAKE, 0);
2452 ath_power_restore_power_state(sc);
2453 ATH_UNLOCK(sc);
2454 DPRINTF(sc, ATH_DEBUG_BEACON,
2460 sc->sc_syncbeacon = 1;
2482 struct ath_softc *sc = arg;
2485 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending);
2487 ATH_LOCK(sc);
2488 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2489 ATH_UNLOCK(sc);
2491 ath_beacon_miss(sc);
2499 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) {
2500 ath_reset(sc, ATH_RESET_NOLOSS, HAL_RESET_BBPANIC);
2501 device_printf(sc->sc_dev,
2504 ath_reset(sc, ATH_RESET_NOLOSS, HAL_RESET_FORCE_COLD);
2505 ieee80211_beacon_miss(&sc->sc_ic);
2509 sc->sc_syncbeacon = 1;
2511 ATH_LOCK(sc);
2512 ath_power_restore_power_state(sc);
2513 ATH_UNLOCK(sc);
2523 ath_settkipmic(struct ath_softc *sc)
2525 struct ieee80211com *ic = &sc->sc_ic;
2527 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) {
2529 ath_hal_settkipmic(sc->sc_ah, AH_FALSE);
2532 ath_hal_settkipmic(sc->sc_ah, AH_TRUE);
2539 ath_vap_clear_quiet_ie(struct ath_softc *sc)
2541 struct ieee80211com *ic = &sc->sc_ic;
2553 ath_init(struct ath_softc *sc)
2555 struct ieee80211com *ic = &sc->sc_ic;
2556 struct ath_hal *ah = sc->sc_ah;
2559 ATH_LOCK_ASSERT(sc);
2564 ath_power_setselfgen(sc, HAL_PM_AWAKE);
2565 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2566 ath_power_setpower(sc, HAL_PM_AWAKE, 1);
2572 ath_stop(sc);
2581 ath_settkipmic(sc);
2582 ath_update_chainmasks(sc, ic->ic_curchan);
2583 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
2584 sc->sc_cur_rxchainmask);
2586 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE,
2588 device_printf(sc->sc_dev,
2593 ATH_RX_LOCK(sc);
2594 sc->sc_rx_stopped = 1;
2595 sc->sc_rx_resetted = 1;
2596 ATH_RX_UNLOCK(sc);
2599 ath_vap_clear_quiet_ie(sc);
2601 ath_chan_change(sc, ic->ic_curchan);
2604 ath_dfs_radar_enable(sc, ic->ic_curchan);
2607 ath_spectral_enable(sc, ic->ic_curchan);
2612 ath_btcoex_enable(sc, ic->ic_curchan);
2618 if (sc->sc_hasenforcetxop && sc->sc_tdma)
2619 ath_hal_setenforcetxop(sc->sc_ah, 1);
2621 ath_hal_setenforcetxop(sc->sc_ah, 0);
2627 sc->sc_diversity = ath_hal_getdiversity(ah);
2628 sc->sc_lastlongcal = ticks;
2629 sc->sc_resetcal = 1;
2630 sc->sc_lastcalreset = 0;
2631 sc->sc_lastani = ticks;
2632 sc->sc_lastshortcal = ticks;
2633 sc->sc_doresetcal = AH_FALSE;
2639 sc->sc_beacons = 0;
2648 if (ath_startrecv(sc) != 0) {
2649 device_printf(sc->sc_dev, "unable to start recv logic\n");
2650 ath_power_restore_power_state(sc);
2657 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
2665 if (sc->sc_isedma)
2666 sc->sc_imask |= (HAL_INT_RXHP | HAL_INT_RXLP);
2673 if (! sc->sc_isedma)
2674 sc->sc_imask |= HAL_INT_RXEOL;
2679 if (sc->sc_btcoex_mci)
2680 sc->sc_imask |= HAL_INT_MCI;
2686 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA)
2687 sc->sc_imask |= HAL_INT_MIB;
2696 sc->sc_imask |= HAL_INT_TSFOOR;
2700 sc->sc_imask |= HAL_INT_GTT;
2702 DPRINTF(sc, ATH_DEBUG_RESET, "%s: imask=0x%x\n",
2703 __func__, sc->sc_imask);
2705 sc->sc_running = 1;
2706 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc);
2707 ath_hal_intrset(ah, sc->sc_imask);
2709 ath_power_restore_power_state(sc);
2715 ath_stop(struct ath_softc *sc)
2717 struct ath_hal *ah = sc->sc_ah;
2719 ATH_LOCK_ASSERT(sc);
2724 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2726 if (sc->sc_running) {
2743 if (sc->sc_tx99 != NULL)
2744 sc->sc_tx99->stop(sc->sc_tx99);
2746 callout_stop(&sc->sc_wd_ch);
2747 sc->sc_wd_timer = 0;
2748 sc->sc_running = 0;
2749 if (!sc->sc_invalid) {
2750 if (sc->sc_softled) {
2751 callout_stop(&sc->sc_ledtimer);
2752 ath_hal_gpioset(ah, sc->sc_ledpin,
2753 !sc->sc_ledon);
2754 sc->sc_blinking = 0;
2759 if (!sc->sc_invalid) {
2760 ath_stoprecv(sc, 1);
2763 sc->sc_rxlink = NULL;
2764 ath_draintxq(sc, ATH_RESET_DEFAULT);
2765 ath_beacon_free(sc); /* XXX not needed */
2769 ath_power_restore_power_state(sc);
2782 ath_txrx_stop_locked(struct ath_softc *sc)
2786 ATH_UNLOCK_ASSERT(sc);
2787 ATH_PCU_LOCK_ASSERT(sc);
2795 while (sc->sc_rxproc_cnt || sc->sc_txproc_cnt ||
2796 sc->sc_txstart_cnt || sc->sc_intr_cnt) {
2799 msleep(sc, &sc->sc_pcu_mtx, 0, "ath_txrx_stop",
2805 device_printf(sc->sc_dev,
2813 ath_txrx_stop(struct ath_softc *sc)
2815 ATH_UNLOCK_ASSERT(sc);
2816 ATH_PCU_UNLOCK_ASSERT(sc);
2818 ATH_PCU_LOCK(sc);
2819 ath_txrx_stop_locked(sc);
2820 ATH_PCU_UNLOCK(sc);
2825 ath_txrx_start(struct ath_softc *sc)
2828 taskqueue_unblock(sc->sc_tq);
2849 ath_reset_grablock(struct ath_softc *sc, int dowait)
2854 ATH_PCU_LOCK_ASSERT(sc);
2856 if (sc->sc_inreset_cnt == 0) {
2864 ATH_PCU_UNLOCK(sc);
2871 ATH_PCU_LOCK(sc);
2879 sc->sc_inreset_cnt++;
2882 device_printf(sc->sc_dev,
2887 device_printf(sc->sc_dev,
2903 ath_reset(struct ath_softc *sc, ATH_RESET_TYPE reset_type,
2906 struct ieee80211com *ic = &sc->sc_ic;
2907 struct ath_hal *ah = sc->sc_ah;
2911 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
2914 ATH_PCU_UNLOCK_ASSERT(sc);
2915 ATH_UNLOCK_ASSERT(sc);
2918 taskqueue_block(sc->sc_tq);
2923 ATH_LOCK(sc);
2924 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2925 ATH_UNLOCK(sc);
2927 ATH_PCU_LOCK(sc);
2935 if (ath_reset_grablock(sc, 1) == 0) {
2936 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
2947 ath_txrx_stop_locked(sc);
2949 ATH_PCU_UNLOCK(sc);
2956 ath_stoprecv(sc, (reset_type != ATH_RESET_NOLOSS));
2957 ath_rx_flush(sc);
2964 ath_draintxq(sc, reset_type); /* stop xmit side */
2966 ath_settkipmic(sc); /* configure TKIP MIC handling */
2968 ath_update_chainmasks(sc, ic->ic_curchan);
2969 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
2970 sc->sc_cur_rxchainmask);
2971 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE,
2973 device_printf(sc->sc_dev,
2976 sc->sc_diversity = ath_hal_getdiversity(ah);
2978 ATH_RX_LOCK(sc);
2979 sc->sc_rx_stopped = 1;
2980 sc->sc_rx_resetted = 1;
2981 ATH_RX_UNLOCK(sc);
2984 ath_vap_clear_quiet_ie(sc);
2987 ath_dfs_radar_enable(sc, ic->ic_curchan);
2990 ath_spectral_enable(sc, ic->ic_curchan);
2995 ath_btcoex_enable(sc, ic->ic_curchan);
3001 if (sc->sc_hasenforcetxop && sc->sc_tdma)
3002 ath_hal_setenforcetxop(sc->sc_ah, 1);
3004 ath_hal_setenforcetxop(sc->sc_ah, 0);
3006 if (ath_startrecv(sc) != 0) /* restart recv */
3007 device_printf(sc->sc_dev,
3014 ath_chan_change(sc, ic->ic_curchan);
3015 if (sc->sc_beacons) { /* restart beacons */
3017 if (sc->sc_tdma)
3018 ath_tdma_config(sc, NULL);
3021 ath_beacon_config(sc, NULL);
3036 ATH_PCU_LOCK(sc);
3037 sc->sc_inreset_cnt--;
3038 sc->sc_txstart_cnt++;
3040 ath_hal_intrset(ah, sc->sc_imask);
3041 ATH_PCU_UNLOCK(sc);
3053 ath_txrx_start(sc);
3060 if (ATH_TXQ_SETUP(sc, i)) {
3061 ATH_TXQ_LOCK(&sc->sc_txq[i]);
3062 ath_txq_restart_dma(sc, &sc->sc_txq[i]);
3063 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
3065 ATH_TX_LOCK(sc);
3066 ath_txq_sched(sc, &sc->sc_txq[i]);
3067 ATH_TX_UNLOCK(sc);
3072 ATH_LOCK(sc);
3073 ath_power_restore_power_state(sc);
3074 ATH_UNLOCK(sc);
3076 ATH_PCU_LOCK(sc);
3077 sc->sc_txstart_cnt--;
3078 ATH_PCU_UNLOCK(sc);
3085 ath_tx_kick(sc); /* restart xmit */
3093 struct ath_softc *sc = ic->ic_softc;
3094 struct ath_hal *ah = sc->sc_ah;
3108 return ath_reset(sc, ATH_RESET_FULL, HAL_RESET_NORMAL);
3112 _ath_getbuf_locked(struct ath_softc *sc, ath_buf_type_t btype)
3116 ATH_TXBUF_LOCK_ASSERT(sc);
3119 bf = TAILQ_FIRST(&sc->sc_txbuf_mgmt);
3121 bf = TAILQ_FIRST(&sc->sc_txbuf);
3124 sc->sc_stats.ast_tx_getnobuf++;
3127 sc->sc_stats.ast_tx_getbusybuf++;
3134 TAILQ_REMOVE(&sc->sc_txbuf_mgmt, bf, bf_list);
3136 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list);
3137 sc->sc_txbuf_cnt--;
3144 if (sc->sc_txbuf_cnt < 0) {
3145 device_printf(sc->sc_dev,
3148 sc->sc_txbuf_cnt = 0;
3156 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__,
3157 TAILQ_FIRST(&sc->sc_txbuf) == NULL ?
3179 if (sc->sc_isedma) {
3180 bf->bf_descid = sc->sc_txbuf_descid;
3181 sc->sc_txbuf_descid++;
3202 ath_buf_clone(struct ath_softc *sc, struct ath_buf *bf)
3206 tbf = ath_getbuf(sc,
3239 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3241 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3254 ath_getbuf(struct ath_softc *sc, ath_buf_type_t btype)
3258 ATH_TXBUF_LOCK(sc);
3259 bf = _ath_getbuf_locked(sc, btype);
3265 bf = _ath_getbuf_locked(sc, ATH_BUFTYPE_NORMAL);
3266 ATH_TXBUF_UNLOCK(sc);
3268 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__);
3269 sc->sc_stats.ast_tx_qstop++;
3283 struct ath_softc *sc = ic->ic_softc;
3293 ATH_PCU_LOCK(sc);
3294 if (sc->sc_inreset_cnt > 0) {
3295 DPRINTF(sc, ATH_DEBUG_XMIT,
3297 ATH_PCU_UNLOCK(sc);
3298 sc->sc_stats.ast_tx_qstop++;
3299 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: OACTIVE, finish");
3302 sc->sc_txstart_cnt++;
3303 ATH_PCU_UNLOCK(sc);
3306 ATH_LOCK(sc);
3307 ath_power_set_power_state(sc, HAL_PM_AWAKE);
3308 ATH_UNLOCK(sc);
3310 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_transmit: start");
3315 ATH_TX_LOCK(sc);
3336 (ATH_NODE(ni)->an_swq_depth > sc->sc_txq_node_maxdepth)) {
3337 sc->sc_stats.ast_tx_nodeq_overflow++;
3359 (sc->sc_txbuf_cnt <= sc->sc_txq_data_minfree)) {
3360 sc->sc_stats.ast_tx_nobuf++;
3376 bf = ath_getbuf(sc, ATH_BUFTYPE_MGMT);
3378 bf = ath_getbuf(sc, ATH_BUFTYPE_NORMAL);
3387 sc->sc_stats.ast_tx_nobuf++;
3405 !ath_txfrag_setup(sc, &frags, m, ni)) {
3406 DPRINTF(sc, ATH_DEBUG_XMIT,
3408 sc->sc_stats.ast_tx_nofrag++;
3477 if (ath_tx_start(sc, ni, bf, m)) {
3483 ATH_TXBUF_LOCK(sc);
3484 ath_returnbuf_head(sc, bf);
3489 ath_txfrag_cleanup(sc, &frags, ni);
3490 ATH_TXBUF_UNLOCK(sc);
3505 ath_tx_update_tim(sc, ni, 1);
3513 DPRINTF(sc, ATH_DEBUG_XMIT,
3531 sc->sc_wd_timer = 5;
3534 ATH_TX_UNLOCK(sc);
3539 ATH_PCU_LOCK(sc);
3540 sc->sc_txstart_cnt--;
3541 ATH_PCU_UNLOCK(sc);
3544 ATH_LOCK(sc);
3545 ath_power_restore_power_state(sc);
3546 ATH_UNLOCK(sc);
3548 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_transmit: finished");
3562 struct ath_softc *sc = vap->iv_ic->ic_softc;
3564 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
3565 taskqueue_block(sc->sc_tq);
3571 struct ath_softc *sc = vap->iv_ic->ic_softc;
3573 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
3574 taskqueue_unblock(sc->sc_tq);
3580 struct ath_softc *sc = ic->ic_softc;
3584 ATH_LOCK(sc);
3585 ath_power_set_power_state(sc, HAL_PM_AWAKE);
3586 rfilt = ath_calcrxfilter(sc);
3587 ath_hal_setrxfilter(sc->sc_ah, rfilt);
3588 ath_power_restore_power_state(sc);
3589 ATH_UNLOCK(sc);
3591 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt);
3600 ath_update_mcast_hw(struct ath_softc *sc)
3602 struct ieee80211com *ic = &sc->sc_ic;
3640 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]);
3642 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n",
3653 struct ath_softc *sc = ic->ic_softc;
3655 ATH_LOCK(sc);
3656 ath_power_set_power_state(sc, HAL_PM_AWAKE);
3657 ATH_UNLOCK(sc);
3659 ath_update_mcast_hw(sc);
3661 ATH_LOCK(sc);
3662 ath_power_restore_power_state(sc);
3663 ATH_UNLOCK(sc);
3667 ath_mode_init(struct ath_softc *sc)
3669 struct ieee80211com *ic = &sc->sc_ic;
3670 struct ath_hal *ah = sc->sc_ah;
3676 rfilt = ath_calcrxfilter(sc);
3686 ath_update_mcast_hw(sc);
3693 ath_setslottime(struct ath_softc *sc)
3695 struct ieee80211com *ic = &sc->sc_ic;
3696 struct ath_hal *ah = sc->sc_ah;
3713 DPRINTF(sc, ATH_DEBUG_RESET,
3719 ATH_LOCK(sc);
3720 ath_power_set_power_state(sc, HAL_PM_AWAKE);
3722 ath_power_restore_power_state(sc);
3723 sc->sc_updateslot = OK;
3724 ATH_UNLOCK(sc);
3734 struct ath_softc *sc = ic->ic_softc;
3745 sc->sc_updateslot = UPDATE;
3747 ath_setslottime(sc);
3778 struct ath_softc *sc = arg;
3781 device_printf(sc->sc_dev, "%s: resetting\n", __func__);
3783 ath_reset(sc, ATH_RESET_NOLOSS, HAL_RESET_FORCE_COLD);
3792 struct ath_softc *sc = arg;
3795 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0)
3796 device_printf(sc->sc_dev, "bb hang detected (0x%x)\n", hangs);
3799 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_STUCK_BEACON))
3800 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_STUCK_BEACON, 0, NULL);
3803 device_printf(sc->sc_dev, "stuck beacon; resetting (bmiss count %u)\n",
3804 sc->sc_bmisscount);
3805 sc->sc_stats.ast_bstuck++;
3810 ath_reset(sc, ATH_RESET_NOLOSS, HAL_RESET_FORCE_COLD);
3814 ath_desc_alloc(struct ath_softc *sc)
3818 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
3819 "tx", sc->sc_tx_desclen, ath_txbuf, ATH_MAX_SCATTER);
3823 sc->sc_txbuf_cnt = ath_txbuf;
3825 error = ath_descdma_setup(sc, &sc->sc_txdma_mgmt, &sc->sc_txbuf_mgmt,
3826 "tx_mgmt", sc->sc_tx_desclen, ath_txbuf_mgmt,
3829 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3838 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
3839 "beacon", sc->sc_tx_desclen, ATH_BCBUF, 1);
3841 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3842 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt,
3843 &sc->sc_txbuf_mgmt);
3850 ath_desc_free(struct ath_softc *sc)
3853 if (sc->sc_bdma.dd_desc_len != 0)
3854 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
3855 if (sc->sc_txdma.dd_desc_len != 0)
3856 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3857 if (sc->sc_txdma_mgmt.dd_desc_len != 0)
3858 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt,
3859 &sc->sc_txbuf_mgmt);
3866 struct ath_softc *sc = ic->ic_softc;
3867 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space;
3875 ath_rate_node_init(sc, an);
3879 device_get_nameunit(sc->sc_dev), an);
3883 ath_tx_tid_init(sc, an);
3889 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__, mac, ":", an);
3897 struct ath_softc *sc = ic->ic_softc;
3899 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__,
3903 ath_tx_node_flush(sc, ATH_NODE(ni));
3904 ath_rate_node_cleanup(sc, ATH_NODE(ni));
3905 sc->sc_node_cleanup(ni);
3912 struct ath_softc *sc = ic->ic_softc;
3914 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__,
3917 sc->sc_node_free(ni);
3924 struct ath_softc *sc = ic->ic_softc;
3925 struct ath_hal *ah = sc->sc_ah;
3938 ath_setdefantenna(struct ath_softc *sc, u_int antenna)
3940 struct ath_hal *ah = sc->sc_ah;
3944 if (sc->sc_defant != antenna)
3945 sc->sc_stats.ast_ant_defswitch++;
3946 sc->sc_defant = antenna;
3947 sc->sc_rxotherant = 0;
3951 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum)
3959 txq->axq_softc = sc;
3963 ATH_TXQ_LOCK_INIT(sc, txq);
3970 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
3972 struct ath_hal *ah = sc->sc_ah;
3993 if (sc->sc_isedma)
4008 if (qnum >= nitems(sc->sc_txq)) {
4009 device_printf(sc->sc_dev,
4011 qnum, nitems(sc->sc_txq));
4015 if (!ATH_TXQ_SETUP(sc, qnum)) {
4016 ath_txq_init(sc, &sc->sc_txq[qnum], qnum);
4017 sc->sc_txqsetup |= 1<<qnum;
4019 return &sc->sc_txq[qnum];
4032 ath_tx_setup(struct ath_softc *sc, int ac, int haltype)
4036 if (ac >= nitems(sc->sc_ac2q)) {
4037 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n",
4038 ac, nitems(sc->sc_ac2q));
4041 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
4044 sc->sc_ac2q[ac] = txq;
4054 ath_txq_update(struct ath_softc *sc, int ac)
4057 struct ieee80211com *ic = &sc->sc_ic;
4058 struct ath_txq *txq = sc->sc_ac2q[ac];
4061 struct ath_hal *ah = sc->sc_ah;
4069 if (sc->sc_tdma) {
4088 qi.tqi_readyTime = sc->sc_tdmaslotlen;
4111 DPRINTF(sc, ATH_DEBUG_RESET,
4117 device_printf(sc->sc_dev, "unable to update hardware queue "
4133 struct ath_softc *sc = ic->ic_softc;
4135 return !ath_txq_update(sc, WME_AC_BE) ||
4136 !ath_txq_update(sc, WME_AC_BK) ||
4137 !ath_txq_update(sc, WME_AC_VI) ||
4138 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0;
4145 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
4148 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum);
4149 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
4157 ath_tx_cleanup(struct ath_softc *sc)
4161 ATH_TXBUF_LOCK_DESTROY(sc);
4163 if (ATH_TXQ_SETUP(sc, i))
4164 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
4172 ath_tx_findrix(const struct ath_softc *sc, uint8_t rate)
4174 int rix = sc->sc_rixmap[rate];
4180 ath_tx_update_stats(struct ath_softc *sc, struct ath_tx_status *ts,
4184 struct ieee80211com *ic = &sc->sc_ic;
4189 sc->sc_stats.ast_ant_tx[txant]++;
4190 sc->sc_ant_tx[txant]++;
4192 sc->sc_stats.ast_tx_altrate++;
4203 sc->sc_stats.ast_tx_xretries++;
4205 sc->sc_stats.ast_tx_fifoerr++;
4207 sc->sc_stats.ast_tx_filtered++;
4209 sc->sc_stats.ast_tx_xtxop++;
4211 sc->sc_stats.ast_tx_timerexpired++;
4214 sc->sc_stats.ast_ff_txerr++;
4218 sc->sc_stats.ast_tx_desccfgerr++;
4228 sc->sc_stats.ast_tx_data_underrun++;
4230 sc->sc_stats.ast_tx_delim_underrun++;
4234 sc->sc_stats.ast_tx_shortretry += sr;
4235 sc->sc_stats.ast_tx_longretry += lr;
4245 ath_tx_default_comp(struct ath_softc *sc, struct ath_buf *bf, int fail)
4258 device_printf(sc->sc_dev,
4265 device_printf(sc->sc_dev,
4287 ATH_TX_LOCK(sc);
4288 ath_tx_update_tim(sc, bf->bf_node, 0);
4289 ATH_TX_UNLOCK(sc);
4298 ath_tx_freebuf(sc, bf, st);
4305 ath_tx_update_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni,
4326 ath_rate_tx_complete(sc, an, rc, ts, frmlen, rc_framelen,
4340 ath_tx_process_buf_completion(struct ath_softc *sc, struct ath_txq *txq,
4345 ATH_TX_UNLOCK_ASSERT(sc);
4351 ath_tx_update_stats(sc, ts, bf);
4372 ath_tx_update_ratectrl(sc, ni,
4379 ath_tx_default_comp(sc, bf, 0);
4381 bf->bf_comp(sc, bf, 0);
4390 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq, int dosched)
4392 struct ath_hal *ah = sc->sc_ah;
4398 struct ieee80211com *ic = &sc->sc_ic;
4403 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
4405 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
4408 ATH_KTR(sc, ATH_KTR_TXCOMP, 4,
4411 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
4429 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
4430 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
4432 else if ((sc->sc_debug & ATH_DEBUG_RESET) && (dosched == 0))
4433 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
4437 if (if_ath_alq_checkdebug(&sc->sc_alq,
4439 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS,
4440 sc->sc_tx_statuslen,
4446 ATH_KTR(sc, ATH_KTR_TXCOMP, 3,
4458 device_printf(sc->sc_dev,
4466 device_printf(sc->sc_dev,
4496 ATH_KTR(sc, ATH_KTR_TXCOMP, 5,
4507 sc->sc_stats.ast_tx_rssi = ts->ts_rssi;
4508 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
4518 ath_tx_process_buf_completion(sc, txq, ts, bf);
4532 ATH_TX_LOCK(sc);
4533 ath_txq_sched(sc, txq);
4534 ATH_TX_UNLOCK(sc);
4537 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4553 struct ath_softc *sc = arg;
4556 ATH_PCU_LOCK(sc);
4557 sc->sc_txproc_cnt++;
4558 txqs = sc->sc_txq_active;
4559 sc->sc_txq_active &= ~txqs;
4560 ATH_PCU_UNLOCK(sc);
4562 ATH_LOCK(sc);
4563 ath_power_set_power_state(sc, HAL_PM_AWAKE);
4564 ATH_UNLOCK(sc);
4566 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4569 if (TXQACTIVE(txqs, 0) && ath_tx_processq(sc, &sc->sc_txq[0], 1))
4571 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4572 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum))
4573 ath_tx_processq(sc, sc->sc_cabq, 1);
4574 sc->sc_wd_timer = 0;
4576 if (sc->sc_softled)
4577 ath_led_event(sc, sc->sc_txrix);
4579 ATH_PCU_LOCK(sc);
4580 sc->sc_txproc_cnt--;
4581 ATH_PCU_UNLOCK(sc);
4583 ATH_LOCK(sc);
4584 ath_power_restore_power_state(sc);
4585 ATH_UNLOCK(sc);
4587 ath_tx_kick(sc);
4597 struct ath_softc *sc = arg;
4601 ATH_PCU_LOCK(sc);
4602 sc->sc_txproc_cnt++;
4603 txqs = sc->sc_txq_active;
4604 sc->sc_txq_active &= ~txqs;
4605 ATH_PCU_UNLOCK(sc);
4607 ATH_LOCK(sc);
4608 ath_power_set_power_state(sc, HAL_PM_AWAKE);
4609 ATH_UNLOCK(sc);
4611 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4619 nacked += ath_tx_processq(sc, &sc->sc_txq[0], 1);
4621 nacked += ath_tx_processq(sc, &sc->sc_txq[1], 1);
4623 nacked += ath_tx_processq(sc, &sc->sc_txq[2], 1);
4625 nacked += ath_tx_processq(sc, &sc->sc_txq[3], 1);
4626 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum))
4627 ath_tx_processq(sc, sc->sc_cabq, 1);
4629 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4631 sc->sc_wd_timer = 0;
4633 if (sc->sc_softled)
4634 ath_led_event(sc, sc->sc_txrix);
4636 ATH_PCU_LOCK(sc);
4637 sc->sc_txproc_cnt--;
4638 ATH_PCU_UNLOCK(sc);
4640 ATH_LOCK(sc);
4641 ath_power_restore_power_state(sc);
4642 ATH_UNLOCK(sc);
4644 ath_tx_kick(sc);
4653 struct ath_softc *sc = arg;
4657 ATH_PCU_LOCK(sc);
4658 sc->sc_txproc_cnt++;
4659 txqs = sc->sc_txq_active;
4660 sc->sc_txq_active &= ~txqs;
4661 ATH_PCU_UNLOCK(sc);
4663 ATH_LOCK(sc);
4664 ath_power_set_power_state(sc, HAL_PM_AWAKE);
4665 ATH_UNLOCK(sc);
4667 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, "ath_tx_proc: txqs=0x%08x", txqs);
4674 if (ATH_TXQ_SETUP(sc, i) && TXQACTIVE(txqs, i))
4675 nacked += ath_tx_processq(sc, &sc->sc_txq[i], 1);
4677 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4679 sc->sc_wd_timer = 0;
4681 if (sc->sc_softled)
4682 ath_led_event(sc, sc->sc_txrix);
4684 ATH_PCU_LOCK(sc);
4685 sc->sc_txproc_cnt--;
4686 ATH_PCU_UNLOCK(sc);
4688 ATH_LOCK(sc);
4689 ath_power_restore_power_state(sc);
4690 ATH_UNLOCK(sc);
4692 ath_tx_kick(sc);
4702 struct ath_softc *sc = arg;
4706 ATH_PCU_LOCK(sc);
4708 if (sc->sc_inreset_cnt > 0) {
4709 device_printf(sc->sc_dev,
4711 ATH_PCU_UNLOCK(sc);
4715 sc->sc_txproc_cnt++;
4716 ATH_PCU_UNLOCK(sc);
4718 ATH_LOCK(sc);
4719 ath_power_set_power_state(sc, HAL_PM_AWAKE);
4720 ATH_UNLOCK(sc);
4722 ATH_TX_LOCK(sc);
4724 if (ATH_TXQ_SETUP(sc, i)) {
4725 ath_txq_sched(sc, &sc->sc_txq[i]);
4728 ATH_TX_UNLOCK(sc);
4730 ATH_LOCK(sc);
4731 ath_power_restore_power_state(sc);
4732 ATH_UNLOCK(sc);
4734 ATH_PCU_LOCK(sc);
4735 sc->sc_txproc_cnt--;
4736 ATH_PCU_UNLOCK(sc);
4740 ath_returnbuf_tail(struct ath_softc *sc, struct ath_buf *bf)
4743 ATH_TXBUF_LOCK_ASSERT(sc);
4746 TAILQ_INSERT_TAIL(&sc->sc_txbuf_mgmt, bf, bf_list);
4748 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
4749 sc->sc_txbuf_cnt++;
4750 if (sc->sc_txbuf_cnt > ath_txbuf) {
4751 device_printf(sc->sc_dev,
4755 sc->sc_txbuf_cnt = ath_txbuf;
4761 ath_returnbuf_head(struct ath_softc *sc, struct ath_buf *bf)
4764 ATH_TXBUF_LOCK_ASSERT(sc);
4767 TAILQ_INSERT_HEAD(&sc->sc_txbuf_mgmt, bf, bf_list);
4769 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
4770 sc->sc_txbuf_cnt++;
4771 if (sc->sc_txbuf_cnt > ATH_TXBUF) {
4772 device_printf(sc->sc_dev,
4776 sc->sc_txbuf_cnt = ATH_TXBUF;
4785 ath_txq_freeholdingbuf(struct ath_softc *sc, struct ath_txq *txq)
4787 ATH_TXBUF_UNLOCK_ASSERT(sc);
4795 ATH_TXBUF_LOCK(sc);
4796 ath_returnbuf_tail(sc, txq->axq_holdingbf);
4797 ATH_TXBUF_UNLOCK(sc);
4807 ath_txq_addholdingbuf(struct ath_softc *sc, struct ath_buf *bf)
4811 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue];
4813 ATH_TXBUF_UNLOCK_ASSERT(sc);
4820 device_printf(sc->sc_dev, "%s: bf=%p: invalid tx queue (%d)\n",
4825 ath_returnbuf_tail(sc, bf);
4828 ath_txq_freeholdingbuf(sc, txq);
4850 ath_freebuf(struct ath_softc *sc, struct ath_buf *bf)
4854 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue];
4864 ath_txq_addholdingbuf(sc, bf);
4872 ATH_TXBUF_LOCK(sc);
4873 ath_returnbuf_tail(sc, bf);
4874 ATH_TXBUF_UNLOCK(sc);
4884 ath_tx_freebuf(struct ath_softc *sc, struct ath_buf *bf, int status)
4895 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
4897 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
4904 ath_freebuf(sc, bf);
4911 ath_tx_draintxq_get_one(struct ath_softc *sc, struct ath_txq *txq)
4929 device_printf(sc->sc_dev,
4945 device_printf(sc->sc_dev,
4966 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
4969 struct ath_hal *ah = sc->sc_ah;
4980 bf = ath_tx_draintxq_get_one(sc, txq);
4988 if (sc->sc_debug & ATH_DEBUG_RESET) {
4989 struct ieee80211com *ic = &sc->sc_ic;
4998 if (! sc->sc_isedma) {
5003 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, status);
5020 bf->bf_comp(sc, bf, 1);
5022 ath_tx_default_comp(sc, bf, 1);
5029 ath_txq_freeholdingbuf(sc, txq);
5036 ath_tx_txq_drain(sc, txq);
5040 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
5042 struct ath_hal *ah = sc->sc_ah;
5046 DPRINTF(sc, ATH_DEBUG_RESET,
5063 if ((sc->sc_debug & ATH_DEBUG_RESET)
5065 ath_printtxbuf(sc, txq->axq_holdingbf, txq->axq_qnum, 0, 0);
5071 ath_stoptxdma(struct ath_softc *sc)
5073 struct ath_hal *ah = sc->sc_ah;
5077 if (sc->sc_invalid)
5080 if (!sc->sc_invalid) {
5082 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
5083 __func__, sc->sc_bhalq,
5084 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq),
5088 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
5092 if (ATH_TXQ_SETUP(sc, i)) {
5093 ATH_TXQ_LOCK(&sc->sc_txq[i]);
5094 ath_tx_stopdma(sc, &sc->sc_txq[i]);
5095 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
5105 ath_tx_dump(struct ath_softc *sc, struct ath_txq *txq)
5107 struct ath_hal *ah = sc->sc_ah;
5111 if (! (sc->sc_debug & ATH_DEBUG_RESET))
5114 device_printf(sc->sc_dev, "%s: Q%d: begin\n",
5117 ath_printtxbuf(sc, bf, txq->axq_qnum, i,
5122 device_printf(sc->sc_dev, "%s: Q%d: end\n",
5131 ath_legacy_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type)
5133 struct ath_hal *ah = sc->sc_ah;
5137 (void) ath_stoptxdma(sc);
5147 if (ATH_TXQ_SETUP(sc, i)) {
5149 if (sc->sc_debug & ATH_DEBUG_RESET)
5150 ath_tx_dump(sc, &sc->sc_txq[i]);
5153 ath_tx_processq(sc, &sc->sc_txq[i], 0);
5154 ATH_TXQ_LOCK(&sc->sc_txq[i]);
5159 ath_txq_freeholdingbuf(sc, &sc->sc_txq[i]);
5166 bf_last = ATH_TXQ_LAST(&sc->sc_txq[i],
5171 &sc->sc_txq[i].axq_link);
5173 sc->sc_txq[i].axq_link = NULL;
5175 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
5177 ath_tx_draintxq(sc, &sc->sc_txq[i]);
5181 if (sc->sc_debug & ATH_DEBUG_RESET) {
5182 struct ath_buf *bf = TAILQ_FIRST(&sc->sc_bbuf);
5184 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0,
5187 ieee80211_dump_pkt(&sc->sc_ic,
5193 sc->sc_wd_timer = 0;
5200 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
5209 if (mode != sc->sc_curmode)
5210 ath_setcurmode(sc, mode);
5211 sc->sc_curchan = chan;
5221 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
5223 struct ieee80211com *ic = &sc->sc_ic;
5224 struct ath_hal *ah = sc->sc_ah;
5228 ATH_PCU_UNLOCK_ASSERT(sc);
5229 ATH_UNLOCK_ASSERT(sc);
5232 taskqueue_block(sc->sc_tq);
5234 ATH_PCU_LOCK(sc);
5240 if (ath_reset_grablock(sc, 1) == 0) {
5241 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
5246 ath_txrx_stop_locked(sc);
5248 ATH_PCU_UNLOCK(sc);
5250 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n",
5253 if (chan != sc->sc_curchan) {
5264 ath_stoprecv(sc, 1); /* turn off frame recv */
5268 ath_rx_flush(sc);
5269 ath_draintxq(sc, ATH_RESET_NOLOSS);
5273 ath_draintxq(sc, ATH_RESET_FULL); /* clear pending tx frames */
5275 ath_update_chainmasks(sc, chan);
5276 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
5277 sc->sc_cur_rxchainmask);
5278 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE,
5280 device_printf(sc->sc_dev, "%s: unable to reset "
5287 sc->sc_diversity = ath_hal_getdiversity(ah);
5289 ATH_RX_LOCK(sc);
5290 sc->sc_rx_stopped = 1;
5291 sc->sc_rx_resetted = 1;
5292 ATH_RX_UNLOCK(sc);
5295 ath_vap_clear_quiet_ie(sc);
5298 ath_dfs_radar_enable(sc, chan);
5301 ath_spectral_enable(sc, chan);
5307 ath_btcoex_enable(sc, ic->ic_curchan);
5313 if (sc->sc_hasenforcetxop && sc->sc_tdma)
5314 ath_hal_setenforcetxop(sc->sc_ah, 1);
5316 ath_hal_setenforcetxop(sc->sc_ah, 0);
5321 if (ath_startrecv(sc) != 0) {
5322 device_printf(sc->sc_dev,
5332 ath_chan_change(sc, chan);
5338 if (sc->sc_beacons) { /* restart beacons */
5340 if (sc->sc_tdma)
5341 ath_tdma_config(sc, NULL);
5344 ath_beacon_config(sc, NULL);
5351 ath_hal_intrset(ah, sc->sc_imask);
5356 ATH_PCU_LOCK(sc);
5357 sc->sc_inreset_cnt--;
5359 ath_hal_intrset(ah, sc->sc_imask);
5360 ATH_PCU_UNLOCK(sc);
5362 ath_txrx_start(sc);
5375 struct ath_softc *sc = arg;
5376 struct ath_hal *ah = sc->sc_ah;
5377 struct ieee80211com *ic = &sc->sc_ic;
5382 ATH_LOCK_ASSERT(sc);
5387 ath_power_set_power_state(sc, HAL_PM_AWAKE);
5390 if (sc->sc_inreset_cnt)
5395 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz);
5396 aniCal = (ticks - sc->sc_lastani >= ath_anicalinterval*hz/1000);
5397 if (sc->sc_doresetcal)
5398 shortCal = (ticks - sc->sc_lastshortcal >= ath_shortcalinterval*hz/1000);
5400 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: shortCal=%d; longCal=%d; aniCal=%d\n", __func__, shortCal, longCal, aniCal);
5402 sc->sc_stats.ast_ani_cal++;
5403 sc->sc_lastani = ticks;
5404 ath_hal_ani_poll(ah, sc->sc_curchan);
5408 sc->sc_stats.ast_per_cal++;
5409 sc->sc_lastlongcal = ticks;
5415 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
5417 sc->sc_stats.ast_per_rfgain++;
5418 sc->sc_resetcal = 0;
5419 sc->sc_doresetcal = AH_TRUE;
5420 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask);
5421 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
5422 ath_power_restore_power_state(sc);
5429 if (sc->sc_resetcal) {
5430 (void) ath_hal_calreset(ah, sc->sc_curchan);
5431 sc->sc_lastcalreset = ticks;
5432 sc->sc_lastshortcal = ticks;
5433 sc->sc_resetcal = 0;
5434 sc->sc_doresetcal = AH_TRUE;
5441 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) {
5449 DPRINTF(sc, ATH_DEBUG_ANY,
5451 __func__, sc->sc_curchan->ic_freq);
5452 sc->sc_stats.ast_per_calfail++;
5469 sc->sc_lastshortcal = ticks;
5481 sc->sc_lastshortcal = ticks;
5483 if (sc->sc_opmode != HAL_M_HOSTAP)
5485 sc->sc_doresetcal = AH_TRUE;
5489 if (sc->sc_lastcalreset == 0)
5490 sc->sc_lastcalreset = sc->sc_lastlongcal;
5491 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz)
5492 sc->sc_resetcal = 1; /* setup reset next trip */
5493 sc->sc_doresetcal = AH_FALSE;
5500 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n",
5502 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc);
5504 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n",
5511 ath_power_restore_power_state(sc);
5517 struct ath_softc *sc = ic->ic_softc;
5518 struct ath_hal *ah = sc->sc_ah;
5524 ATH_LOCK(sc);
5525 sc->sc_scanning = 1;
5526 sc->sc_syncbeacon = 0;
5527 rfilt = ath_calcrxfilter(sc);
5528 ATH_UNLOCK(sc);
5530 ATH_PCU_LOCK(sc);
5533 ATH_PCU_UNLOCK(sc);
5535 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n",
5542 struct ath_softc *sc = ic->ic_softc;
5543 struct ath_hal *ah = sc->sc_ah;
5546 ATH_LOCK(sc);
5547 sc->sc_scanning = 0;
5548 rfilt = ath_calcrxfilter(sc);
5549 ATH_UNLOCK(sc);
5551 ATH_PCU_LOCK(sc);
5553 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5556 ATH_PCU_UNLOCK(sc);
5558 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5559 __func__, rfilt, ether_sprintf(sc->sc_curbssid),
5560 sc->sc_curaid);
5582 struct ath_softc *sc = ic->ic_softc;
5584 //DPRINTF(sc, ATH_DEBUG_STATE, "%s: called\n", __func__);
5585 device_printf(sc->sc_dev, "%s: called\n", __func__);
5635 struct ath_softc *sc = ic->ic_softc;
5642 DPRINTF(sc, ATH_DEBUG_QUIETIE,
5645 ath_hal_set_quiet(sc->sc_ah, 0, 0, 0, HAL_QUIET_DISABLE);
5668 DPRINTF(sc, ATH_DEBUG_QUIETIE,
5681 DPRINTF(sc, ATH_DEBUG_QUIETIE,
5691 DPRINTF(sc, ATH_DEBUG_QUIETIE,
5698 DPRINTF(sc, ATH_DEBUG_QUIETIE,
5703 DPRINTF(sc, ATH_DEBUG_QUIETIE,
5713 DPRINTF(sc, ATH_DEBUG_QUIETIE,
5715 ath_hal_set_quiet(sc->sc_ah,
5735 struct ath_softc *sc = ic->ic_softc;
5737 ATH_LOCK(sc);
5738 ath_power_set_power_state(sc, HAL_PM_AWAKE);
5739 ATH_UNLOCK(sc);
5741 (void) ath_chan_set(sc, ic->ic_curchan);
5748 ATH_LOCK(sc);
5749 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan)
5750 sc->sc_syncbeacon = 1;
5751 ath_power_restore_power_state(sc);
5752 ATH_UNLOCK(sc);
5777 struct ath_softc *sc = ic->ic_softc;
5779 struct ath_hal *ah = sc->sc_ah;
5797 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__,
5811 ATH_LOCK(sc);
5821 ath_power_setselfgen(sc, HAL_PM_AWAKE);
5826 ath_power_set_power_state(sc, HAL_PM_AWAKE);
5832 callout_stop(&sc->sc_cal_ch);
5833 ATH_UNLOCK(sc);
5849 ATH_LOCK(sc);
5850 ath_power_setselfgen(sc, HAL_PM_AWAKE);
5851 ath_power_setpower(sc, HAL_PM_AWAKE, 1);
5852 ATH_UNLOCK(sc);
5855 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS));
5856 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
5857 sc->sc_beacons = 0;
5858 taskqueue_unblock(sc->sc_tq);
5862 rfilt = ath_calcrxfilter(sc);
5872 sc->sc_curaid = ni->ni_associd;
5873 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid);
5874 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5876 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5877 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid);
5956 DPRINTF(sc, ATH_DEBUG_STATE,
5989 ath_hal_stoptxdma(ah, sc->sc_bhalq);
5991 error = ath_beacon_alloc(sc, ni);
6004 sc->sc_syncbeacon = 1;
6005 } else if (!sc->sc_beacons) {
6008 ath_tdma_config(sc, vap);
6011 ath_beacon_config(sc, vap);
6012 sc->sc_beacons = 1;
6033 DPRINTF(sc, ATH_DEBUG_BEACON,
6035 sc->sc_syncbeacon = 1;
6041 ath_beacon_config(sc, vap);
6055 sc->sc_beacons = 1;
6064 ath_hal_intrset(ah, sc->sc_imask);
6079 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
6080 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
6081 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
6086 ATH_LOCK(sc);
6087 ath_power_setselfgen(sc, HAL_PM_AWAKE);
6088 ath_power_setpower(sc, HAL_PM_AWAKE, 1);
6096 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
6098 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
6101 ATH_UNLOCK(sc);
6103 taskqueue_unblock(sc->sc_tq);
6116 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
6118 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);
6119 taskqueue_block(sc->sc_tq);
6120 sc->sc_beacons = 0;
6139 if (sc->sc_nvaps == 1 &&
6141 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: syncbeacon=%d\n", __func__, sc->sc_syncbeacon);
6142 ATH_LOCK(sc);
6147 ath_power_setselfgen(sc, HAL_PM_NETWORK_SLEEP);
6157 if (sc->sc_syncbeacon == 0) {
6158 ath_power_setpower(sc, HAL_PM_NETWORK_SLEEP, 1);
6160 ATH_UNLOCK(sc);
6186 ATH_LOCK(sc);
6189 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
6191 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
6194 ATH_UNLOCK(sc);
6203 ATH_LOCK(sc);
6204 ath_power_restore_power_state(sc);
6205 ATH_UNLOCK(sc);
6221 struct ath_softc *sc = vap->iv_ic->ic_softc;
6240 ath_keyset(sc, vap, &ni->ni_ucastkey, vap->iv_bss);
6254 struct ath_softc *sc = vap->iv_ic->ic_softc;
6257 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate);
6258 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate);
6260 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: reassoc; isnew=%d, is_powersave=%d\n",
6268 ath_rate_newassoc(sc, an, isnew);
6272 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey &&
6286 DPRINTF(sc, ATH_DEBUG_NODE,
6294 ath_tx_node_reassoc(sc, an);
6298 ath_tx_node_wakeup(sc, an);
6306 struct ath_softc *sc = ic->ic_softc;
6307 struct ath_hal *ah = sc->sc_ah;
6310 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
6318 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n",
6330 struct ath_softc *sc = ic->ic_softc;
6331 struct ath_hal *ah = sc->sc_ah;
6333 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n",
6343 ath_getchannels(struct ath_softc *sc)
6345 struct ieee80211com *ic = &sc->sc_ic;
6346 struct ath_hal *ah = sc->sc_ah;
6355 device_printf(sc->sc_dev,
6360 (void) ath_hal_getregdomain(ah, &sc->sc_eerd);
6361 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */
6364 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd;
6365 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc;
6372 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
6374 __func__, sc->sc_eerd, sc->sc_eecc,
6381 ath_rate_setup(struct ath_softc *sc, u_int mode)
6383 struct ath_hal *ah = sc->sc_ah;
6418 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n",
6422 sc->sc_rates[mode] = rt;
6427 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
6454 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
6455 rt = sc->sc_rates[mode];
6460 sc->sc_rixmap[ieeerate] = i;
6462 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i;
6464 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap));
6465 for (i = 0; i < nitems(sc->sc_hwmap); i++) {
6467 sc->sc_hwmap[i].ledon = (500 * hz) / 1000;
6468 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000;
6471 sc->sc_hwmap[i].ieeerate =
6474 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS;
6475 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
6478 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE;
6479 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags;
6481 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate)
6485 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000;
6486 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000;
6488 sc->sc_currates = rt;
6489 sc->sc_curmode = mode;
6495 sc->sc_protrix = ath_tx_findrix(sc, 2*2);
6497 sc->sc_protrix = ath_tx_findrix(sc, 2*1);
6504 struct ath_softc *sc = arg;
6505 struct ieee80211com *ic = &sc->sc_ic;
6508 ATH_LOCK_ASSERT(sc);
6510 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) {
6513 ath_power_set_power_state(sc, HAL_PM_AWAKE);
6515 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) &&
6517 device_printf(sc->sc_dev, "%s hang detected (0x%x)\n",
6520 device_printf(sc->sc_dev, "device timeout\n");
6523 sc->sc_stats.ast_watchdog++;
6525 ath_power_restore_power_state(sc);
6535 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask);
6538 callout_schedule(&sc->sc_wd_ch, hz);
6544 struct ath_softc *sc = ic->ic_softc;
6547 ATH_LOCK(sc);
6554 if (sc->sc_running) {
6555 ath_power_set_power_state(sc, HAL_PM_AWAKE);
6556 ath_mode_init(sc);
6557 ath_power_restore_power_state(sc);
6558 } else if (!sc->sc_invalid) {
6568 error = ath_init(sc);
6571 ath_stop(sc);
6572 if (!sc->sc_invalid)
6573 ath_power_setpower(sc, HAL_PM_FULL_SLEEP, 1);
6575 ATH_UNLOCK(sc);
6579 if (sc->sc_tx99 != NULL)
6580 sc->sc_tx99->start(sc->sc_tx99);
6591 ath_announce(struct ath_softc *sc)
6593 struct ath_hal *ah = sc->sc_ah;
6595 device_printf(sc->sc_dev, "%s mac %d.%d RF%s phy %d.%d\n",
6598 device_printf(sc->sc_dev, "2GHz radio: 0x%.4x; 5GHz radio: 0x%.4x\n",
6603 struct ath_txq *txq = sc->sc_ac2q[i];
6604 device_printf(sc->sc_dev,
6608 device_printf(sc->sc_dev, "Use hw queue %u for CAB traffic\n",
6609 sc->sc_cabq->axq_qnum);
6610 device_printf(sc->sc_dev, "Use hw queue %u for beacons\n",
6611 sc->sc_bhalq);
6614 device_printf(sc->sc_dev, "using %u rx buffers\n", ath_rxbuf);
6616 device_printf(sc->sc_dev, "using %u tx buffers\n", ath_txbuf);
6617 if (sc->sc_mcastkey && bootverbose)
6618 device_printf(sc->sc_dev, "using multicast key search\n");
6624 struct ath_softc *sc = (struct ath_softc *) p;
6625 struct ieee80211com *ic = &sc->sc_ic;
6632 if (ath_dfs_process_radar_event(sc, sc->sc_curchan)) {
6649 ieee80211_dfs_notify_radar(ic, sc->sc_curchan);
6666 struct ath_softc *sc = ic->ic_softc;
6671 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, "%s: %6D: enable=%d\n",
6679 ath_tx_node_sleep(sc, an);
6681 ath_tx_node_wakeup(sc, an);
6733 struct ath_softc *sc = ic->ic_softc;
6738 ATH_TX_LOCK(sc);
6749 ATH_TX_UNLOCK(sc);
6768 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6774 ATH_TX_UNLOCK(sc);
6776 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6783 ATH_TX_UNLOCK(sc);
6787 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6794 ATH_TX_UNLOCK(sc);
6800 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6807 ATH_TX_UNLOCK(sc);
6815 ATH_TX_UNLOCK(sc);
6816 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6862 ath_tx_update_tim(struct ath_softc *sc, struct ieee80211_node *ni,
6883 ATH_TX_LOCK_ASSERT(sc);
6889 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6908 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6938 struct ath_softc *sc = ic->ic_softc;
6983 ATH_TX_LOCK(sc);
6990 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6995 ATH_TX_UNLOCK(sc);
7015 ATH_TX_UNLOCK(sc);
7016 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7036 ath_tx_tid_sched(sc, atid);
7042 ATH_TX_UNLOCK(sc);
7043 taskqueue_enqueue(sc->sc_tq, &sc->sc_txqtask);
7044 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7053 ATH_TX_UNLOCK(sc);
7058 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,