ath_hal/ar9002/ar9285_reset.c

80     MODAL_EEP4K_HEADER	*pModal;
103     pModal = &pEepData->modalHeader;
108         AH5416(ah)->ah_ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
191 ar9285SetBoardGain(struct ath_hal *ah, const MODAL_EEP4K_HEADER *pModal,
195 		  pModal->antCtrlChain[0]);
201 		  SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
202 		  SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
206 		txRxAttenLocal = pModal->txRxAttenCh[0];
209 		    AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
211 		    AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
213 		    AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, pModal->xatten2Margin[0]);
215 		    AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
220 		      pModal->bswMargin[0]);
222 		      AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
225 		      pModal->xatten2Margin[0]);
227 		      AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
233 		      AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
238 		      AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
250 	const MODAL_EEP4K_HEADER *pModal;
254 	pModal = &eep->modalHeader;
257 	OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
260 	ar9285SetBoardGain(ah, pModal, eep, txRxAttenLocal);
266 	if (pModal->version >= 2) {
267 		ob[0] = pModal->ob_0;
268 		ob[1] = pModal->ob_1;
269 		ob[2] = pModal->ob_2;
270 		ob[3] = pModal->ob_3;
271 		ob[4] = pModal->ob_4;
273 		db1[0] = pModal->db1_0;
274 		db1[1] = pModal->db1_1;
275 		db1[2] = pModal->db1_2;
276 		db1[3] = pModal->db1_3;
277 		db1[4] = pModal->db1_4;
279 		db2[0] = pModal->db2_0;
280 		db2[1] = pModal->db2_1;
281 		db2[2] = pModal->db2_2;
282 		db2[3] = pModal->db2_3;
283 		db2[4] = pModal->db2_4;
284 	} else if (pModal->version == 1) {
285 		ob[0] = pModal->ob_0;
286 		ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1;
287 		db1[0] = pModal->db1_0;
288 		db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1;
289 		db2[0] = pModal->db2_0;
290 		db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1;
295 			ob[i] = pModal->ob_0;
296 			db1[i] = pModal->db1_0;
297 			db2[i] = pModal->db1_0;
320 		      pModal->switchSettling);
322 		      pModal->adcDesiredSize);
325 		  SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
326 		  SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
327 		  SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)  |
328 		  SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
331 		      pModal->txEndToRxOn);
334 		      pModal->thresh62);
336 		      pModal->thresh62);
341 		    pModal->txFrameToDataStart);
343 		    pModal->txFrameToPaOn);
350 			    AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
365 		uint8_t bb_desired_scale = (pModal->bb_scale_smrt_antenna & EEP_4K_BB_DESIRED_SCALE_MASK);