ath_hal/ar9002/ar9285_cal.c

31 #include "ah.h"
51 ar9285_hw_pa_cal(struct ath_hal *ah, HAL_BOOL is_reset)
67 	if (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL) ==
71 	HALDEBUG(ah, HAL_DEBUG_PERCAL, "Running PA Calibration\n");
74 		regList[i][1] = OS_REG_READ(ah, regList[i][0]);
76 	regVal = OS_REG_READ(ah, 0x7834);
78 	OS_REG_WRITE(ah, 0x7834, regVal);
79 	regVal = OS_REG_READ(ah, 0x9808);
81 	OS_REG_WRITE(ah, 0x9808, regVal);
83 	OS_REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
84 	OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
85 	OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
86 	OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
87 	OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
88 	OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
89 	OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
90 	OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
91 	OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
92 	OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
93 	OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
94 	OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
95 	ccomp_org = MS(OS_REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
96 	OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
98 	OS_REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
100 	OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
101 	OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
104 		regVal = OS_REG_READ(ah, 0x7834);
106 		OS_REG_WRITE(ah, 0x7834, regVal);
108 		regVal = OS_REG_READ(ah, 0x7834);
110 		reg_field = MS(OS_REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
112 		OS_REG_WRITE(ah, 0x7834, regVal);
115 	OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
117 	reg_field = MS(OS_REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
118 	OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
119 	offs_6_1 = MS(OS_REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
120 	offs_0   = MS(OS_REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
127 	if ((!is_reset) && (AH9285(ah)->pacal_info.prev_offset == offset)) {
128 		if (AH9285(ah)->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
129 			AH9285(ah)->pacal_info.max_skipcount =
130 				2 * AH9285(ah)->pacal_info.max_skipcount;
131 		AH9285(ah)->pacal_info.skipcount = AH9285(ah)->pacal_info.max_skipcount;
133 		AH9285(ah)->pacal_info.max_skipcount = 1;
134 		AH9285(ah)->pacal_info.skipcount = 0;
135 		AH9285(ah)->pacal_info.prev_offset = offset;
138 	OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
139 	OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
141 	regVal = OS_REG_READ(ah, 0x7834);
143 	OS_REG_WRITE(ah, 0x7834, regVal);
144 	regVal = OS_REG_READ(ah, 0x9808);
146 	OS_REG_WRITE(ah, 0x9808, regVal);
149 		OS_REG_WRITE(ah, regList[i][0], regList[i][1]);
151 	OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
155 ar9002_hw_pa_cal(struct ath_hal *ah, HAL_BOOL is_reset)
157 	if (AR_SREV_KITE_11_OR_LATER(ah)) {
158 		if (is_reset || !AH9285(ah)->pacal_info.skipcount)
159 			ar9285_hw_pa_cal(ah, is_reset);
161 			AH9285(ah)->pacal_info.skipcount--;
167 ar9285_hw_cl_cal(struct ath_hal *ah, const struct ieee80211_channel *chan)
169 	OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
171 		OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
172 		OS_REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
173 		OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
175 		OS_REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
176 		OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
177 		if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL,
179 			HALDEBUG(ah, HAL_DEBUG_PERCAL,
183 		OS_REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
184 		OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
185 		OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
187 	OS_REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
188 	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
189 	OS_REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
190 	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
191 	if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
193 		HALDEBUG(ah, HAL_DEBUG_PERCAL,
198 	OS_REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
199 	OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
200 	OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
206 ar9285_hw_clc(struct ath_hal *ah, const struct ieee80211_channel *chan)
218 	if (!(ar9285_hw_cl_cal(ah, chan)))
221 	txgain_max = MS(OS_REG_READ(ah, AR_PHY_TX_PWRCTRL7),
225 		clc_gain = (OS_REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
234 		reg_clc_I0 = (OS_REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
236 		reg_clc_Q0 = (OS_REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
246 		reg_rf2g5_org = OS_REG_READ(ah, AR9285_RF2G5);
247 		if (AR_SREV_9285E_20(ah)) {
248 			OS_REG_WRITE(ah, AR9285_RF2G5,
252 			OS_REG_WRITE(ah, AR9285_RF2G5,
256 		retv = ar9285_hw_cl_cal(ah, chan);
257 		OS_REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
263 ar9285InitCalHardware(struct ath_hal *ah,
266 	if (AR_SREV_KITE(ah) && AR_SREV_KITE_10_OR_LATER(ah) &&
267 	    (! ar9285_hw_clc(ah, chan)))