Lines Matching refs:tx
517 OS_MEMZERO(ads->u.tx.status, sizeof(ads->u.tx.status));
823 /* handle tx trigger level changes internally */
837 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad global tx timeout %u\n",
938 /* Modify the tx power field for rate 0 */
1121 * Allocate and initialize a tx DCU/QCU combination.
1166 "%s: no available UAPSD tx queue\n", __func__);
1176 "%s: no available tx queue\n", __func__);
1182 "%s: bad tx queue type %u\n", __func__, type);
1190 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: tx queue %u already active\n",
1213 * Update the h/w interrupt registers to reflect a tx q's configuration.
1221 "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", __func__,
1471 * Since we don't differentiate between tx interrupts corresponding
1472 * to individual queues - secondary tx mask regs are always unmasked;
1473 * tx interrupts are enabled/disabled for all queues collectively