ath_hal/ar5416/ar5416_xmit.c

1128 	HAL_TX_QUEUE_INFO *qi;
1188 	qi = &ahp->ah_txq[q];
1189 	if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) {
1194 	OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO));
1195 	qi->tqi_type = type;
1197 		qi->tqi_qflags = defqflags;
1198 		qi->tqi_aifs = INIT_AIFS;
1199 		qi->tqi_cwmin = HAL_TXQ_USEDEFAULT;	/* NB: do at reset */
1200 		qi->tqi_cwmax = INIT_CWMAX;
1201 		qi->tqi_shretry = INIT_SH_RETRY;
1202 		qi->tqi_lgretry = INIT_LG_RETRY;
1203 		qi->tqi_physCompBuf = 0;
1205 		qi->tqi_physCompBuf = qInfo->tqi_compBuf;
1216 setTxQInterrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)
1250 	HAL_TX_QUEUE_INFO *qi;
1258 	qi = &ahp->ah_txq[q];
1259 	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
1267 	if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) {
1280 		cwMin = qi->tqi_cwmin;
1285 		| SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
1286 		| SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
1292 		 | SM(qi->tqi_lgretry, AR_D_RETRY_LIMIT_FR_LG)
1293 		 | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)
1313 	if (qi->tqi_cbrPeriod) {
1315 			  SM(qi->tqi_cbrPeriod,AR_Q_CBRCFG_CBR_INTERVAL)
1316 			| SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_CBR_OVF_THRESH));
1318 		if (qi->tqi_cbrOverflowLimit)
1322 	if (qi->tqi_readyTime && (qi->tqi_type != HAL_TX_QUEUE_CAB)) {
1324 			  SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_INT)
1329 		  SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR)
1330 		| (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
1332 	if (qi->tqi_readyTime &&
1333 	    (qi->tqi_qflags & HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE))
1335 	if (qi->tqi_qflags & HAL_TXQ_DBA_GATED)
1341 		if (qi->tqi_qflags & HAL_TXQ_CBR_DIS_BEMPTY)
1345 		if (qi->tqi_qflags & HAL_TXQ_CBR_DIS_QEMPTY)
1351 	if (qi->tqi_qflags & HAL_TXQ_BACKOFF_DISABLE)
1353 	if (qi->tqi_qflags & HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE)
1355 	if (qi->tqi_qflags & HAL_TXQ_ARB_LOCKOUT_GLOBAL)
1358 	else if (qi->tqi_qflags & HAL_TXQ_ARB_LOCKOUT_INTRA)
1361 	if (qi->tqi_qflags & HAL_TXQ_IGNORE_VIRTCOL)
1364 	if (qi->tqi_qflags & HAL_TXQ_SEQNUM_INC_DIS)
1372 	switch (qi->tqi_type) {
1394 		    __func__, qi->tqi_readyTime);
1395 		if (qi->tqi_readyTime) {
1399 			    SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_INT) |
1455 	if (qi->tqi_physCompBuf) {
1456 		HALASSERT(qi->tqi_type == HAL_TX_QUEUE_DATA ||
1457 			  qi->tqi_type == HAL_TX_QUEUE_UAPSD);
1459 		OS_REG_WRITE(ah, AR_Q_CBBA, qi->tqi_physCompBuf);
1476 	if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE)
1480 	if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE)
1484 	if (qi->tqi_qflags & HAL_TXQ_TXDESCINT_ENABLE)
1488 	if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE)
1492 	if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE)
1496 	setTxQInterrupts(ah, qi);