ath_hal/ar5416/ar5416_xmit.c

720 	struct ath_desc *ds, struct ath_tx_status *ts)
735 	ts->ts_seqnum = MS(ds_txstatus[9], AR_SeqNum);
736 	ts->ts_tstamp = AR_SendTimestamp(ds_txstatus);
737 	ts->ts_tid = MS(ds_txstatus[9], AR_TxTid);
739 	ts->ts_status = 0;
741 		ts->ts_status |= HAL_TXERR_XRETRY;
743 		ts->ts_status |= HAL_TXERR_FILT;
745 		ts->ts_status |= HAL_TXERR_FIFO;
747 		ts->ts_status |= HAL_TXERR_XTXOP;
749 		ts->ts_status |= HAL_TXERR_TIMER_EXPIRED;
751 	ts->ts_flags  = 0;
753 		ts->ts_flags |= HAL_TX_BA;
754 		ts->ts_ba_low = AR_BaBitmapLow(ds_txstatus);
755 		ts->ts_ba_high = AR_BaBitmapHigh(ds_txstatus);
758 		ts->ts_flags |= HAL_TX_AGGR;
760 		ts->ts_flags |= HAL_TX_DESC_CFG_ERR;
762 		ts->ts_flags |= HAL_TX_DATA_UNDERRUN;
764 		ts->ts_flags |= HAL_TX_DELIM_UNDERRUN;
770 	ts->ts_finaltsi =  MS(ds_txstatus[9], AR_FinalTxIdx);
771 	switch (ts->ts_finaltsi) {
773 		ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate0);
776 		ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate1);
779 		ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate2);
782 		ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate3);
786 	ts->ts_rssi = MS(ds_txstatus[5], AR_TxRSSICombined);
787 	ts->ts_rssi_ctl[0] = MS(ds_txstatus[0], AR_TxRSSIAnt00);
788 	ts->ts_rssi_ctl[1] = MS(ds_txstatus[0], AR_TxRSSIAnt01);
789 	ts->ts_rssi_ctl[2] = MS(ds_txstatus[0], AR_TxRSSIAnt02);
790 	ts->ts_rssi_ext[0] = MS(ds_txstatus[5], AR_TxRSSIAnt10);
791 	ts->ts_rssi_ext[1] = MS(ds_txstatus[5], AR_TxRSSIAnt11);
792 	ts->ts_rssi_ext[2] = MS(ds_txstatus[5], AR_TxRSSIAnt12);
793 	ts->ts_evm0 = AR_TxEVM0(ds_txstatus);
794 	ts->ts_evm1 = AR_TxEVM1(ds_txstatus);
795 	ts->ts_evm2 = AR_TxEVM2(ds_txstatus);
797 	ts->ts_shortretry = MS(ds_txstatus[1], AR_RTSFailCnt);
798 	ts->ts_longretry = MS(ds_txstatus[1], AR_DataFailCnt);
810 	switch (ts->ts_finaltsi) {
811 	case 3: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries2);
812 	case 2: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries1);
813 	case 1: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries0);
820 	ts->ts_virtcol = MS(ads->ds_ctl1, AR_VirtRetryCnt);
821 	ts->ts_antenna = 0; /* We don't switch antennas on Owl*/
824 	if ((ts->ts_status & HAL_TXERR_FIFO) ||
825 	    (ts->ts_flags & (HAL_TX_DATA_UNDERRUN | HAL_TX_DELIM_UNDERRUN)))