ath_hal/ar5416/ar5416_reset.c

1064     MODAL_EEP_HEADER	*pModal;
1090     pModal = &pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)];
1095         AH5416(ah)->ah_ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1231         POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1232           | POW_SM(pModal->pwrDecreaseFor2Chain, 0)
1540     const MODAL_EEP_HEADER *pModal,
1546 		txRxAttenLocal = pModal->txRxAttenCh[i];
1551 			      pModal->bswMargin[i]);
1554 			      pModal->bswAtten[i]);
1557 			      pModal->xatten2Margin[i]);
1560 			      pModal->xatten2Db[i]);
1564 			      pModal->bswMargin[i]);
1567 			      pModal->bswAtten[i]);
1577 		      AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
1584 			  AR_PHY_GAIN_2GHZ_RXTX_MARGIN, pModal->rxTxMarginCh[i]);
1624     const MODAL_EEP_HEADER *pModal;
1629     pModal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)];
1634     OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
1641         OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, pModal->antCtrlChain[i]);
1646         	SM(pModal->iqCalICh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1647         	SM(pModal->iqCalQCh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1652 	 * txRxAttenLocal = pModal->txRxAttenCh[i]
1657 	    ar5416SetDefGainValues(ah, pModal, eep, txRxAttenLocal, regChainOffset, i);
1662                         OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0, AR_AN_RF2G1_CH0_OB, pModal->ob);
1663                         OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0, AR_AN_RF2G1_CH0_DB, pModal->db);
1664                         OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH1, AR_AN_RF2G1_CH1_OB, pModal->ob_ch1);
1665                         OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH1, AR_AN_RF2G1_CH1_DB, pModal->db_ch1);
1667                         OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH0, AR_AN_RF5G1_CH0_OB5, pModal->ob);
1668                         OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH0, AR_AN_RF5G1_CH0_DB5, pModal->db);
1669                         OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH1, AR_AN_RF5G1_CH1_OB5, pModal->ob_ch1);
1670                         OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH1, AR_AN_RF5G1_CH1_DB5, pModal->db_ch1);
1672                 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP2, AR_AN_TOP2_XPABIAS_LVL, pModal->xpaBiasLvl);
1674 		    !!(pModal->flagBits & AR5416_EEP_FLAG_LOCALBIAS));
1676 		    !!(pModal->flagBits & AR5416_EEP_FLAG_FORCEXPAON));
1679     OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
1680     OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
1683     	OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize);
1686         SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
1687         | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
1688         | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
1689         | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1692 	pModal->txEndToRxOn);
1696 	    pModal->thresh62);
1698 	    pModal->thresh62);
1701 	    pModal->thresh62);
1703 	    pModal->thresh62);
1709 	    pModal->txFrameToDataStart);
1711 	    pModal->txFrameToPaOn);
1717 		    pModal->swSettleHt40);
1720          OS_REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK, pModal->miscBits);
1735 		    pModal->miscBits >> 2);
2714 #define	XPA_LVL_FREQ(cnt)	(pModal->xpaBiasLvlFreq[cnt])
2715 	MODAL_EEP_HEADER	*pModal;
2726 	pModal = &(eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)]);
2728 	if (pModal->xpaBiasLvl != 0xff)
2729 		biaslevel = pModal->xpaBiasLvl;