ath_hal/ar5212/ar5212_xmit.c

126 	HAL_TX_QUEUE_INFO *qi;
178 	qi = &ahp->ah_txq[q];
179 	if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) {
184 	OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO));
185 	qi->tqi_type = type;
187 		qi->tqi_qflags = defqflags;
188 		qi->tqi_aifs = INIT_AIFS;
189 		qi->tqi_cwmin = HAL_TXQ_USEDEFAULT;	/* NB: do at reset */
190 		qi->tqi_cwmax = INIT_CWMAX;
191 		qi->tqi_shretry = INIT_SH_RETRY;
192 		qi->tqi_lgretry = INIT_LG_RETRY;
193 		qi->tqi_physCompBuf = 0;
195 		qi->tqi_physCompBuf = qInfo->tqi_compBuf;
206 setTxQInterrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)
236 	HAL_TX_QUEUE_INFO *qi;
243 	qi = &ahp->ah_txq[q];
244 	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
252 	qi->tqi_type = HAL_TX_QUEUE_INACTIVE;
258 	setTxQInterrupts(ah, qi);
275 	HAL_TX_QUEUE_INFO *qi;
283 	qi = &ahp->ah_txq[q];
284 	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
292 	if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) {
305 		cwMin = qi->tqi_cwmin;
310 		| SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
311 		| SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
317 		 | SM(qi->tqi_lgretry, AR_D_RETRY_LIMIT_FR_LG)
318 		 | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)
335 	if (qi->tqi_cbrPeriod) {
337 			  SM(qi->tqi_cbrPeriod,AR_Q_CBRCFG_CBR_INTERVAL)
338 			| SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_CBR_OVF_THRESH));
340 		if (qi->tqi_cbrOverflowLimit)
343 	if (qi->tqi_readyTime) {
345 			  SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_INT)
350 		  SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR)
351 		| (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
353 	if (qi->tqi_readyTime &&
354 	    (qi->tqi_qflags & HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE))
356 	if (qi->tqi_qflags & HAL_TXQ_DBA_GATED)
362 		if (qi->tqi_qflags & HAL_TXQ_CBR_DIS_BEMPTY)
366 		if (qi->tqi_qflags & HAL_TXQ_CBR_DIS_QEMPTY)
372 	if (qi->tqi_qflags & HAL_TXQ_BACKOFF_DISABLE)
374 	if (qi->tqi_qflags & HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE)
376 	if (qi->tqi_qflags & HAL_TXQ_ARB_LOCKOUT_GLOBAL)
379 	else if (qi->tqi_qflags & HAL_TXQ_ARB_LOCKOUT_INTRA)
382 	if (qi->tqi_qflags & HAL_TXQ_IGNORE_VIRTCOL)
385 	if (qi->tqi_qflags & HAL_TXQ_SEQNUM_INC_DIS)
393 	switch (qi->tqi_type) {
415 		if (qi->tqi_readyTime) {
419 			    SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_INT) |
465 	if (qi->tqi_physCompBuf) {
466 		HALASSERT(qi->tqi_type == HAL_TX_QUEUE_DATA ||
467 			  qi->tqi_type == HAL_TX_QUEUE_UAPSD);
469 		OS_REG_WRITE(ah, AR_Q_CBBA, qi->tqi_physCompBuf);
486 	if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE)
490 	if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE)
494 	if (qi->tqi_qflags & HAL_TXQ_TXDESCINT_ENABLE)
498 	if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE)
502 	if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE)
506 	setTxQInterrupts(ah, qi);