Lines Matching defs:ts
879 struct ath_desc *ds, struct ath_tx_status *ts)
894 ts->ts_seqnum = MS(ads->ds_txstatus1, AR_SeqNum);
895 ts->ts_tstamp = MS(ads->ds_txstatus0, AR_SendTimestamp);
896 ts->ts_status = 0;
899 ts->ts_status |= HAL_TXERR_XRETRY;
901 ts->ts_status |= HAL_TXERR_FILT;
903 ts->ts_status |= HAL_TXERR_FIFO;
909 ts->ts_finaltsi = MS(ads->ds_txstatus1, AR_FinalTSIndex);
910 switch (ts->ts_finaltsi) {
912 ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate0);
915 ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate1);
918 ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate2);
921 ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate3);
924 ts->ts_rssi = MS(ads->ds_txstatus1, AR_AckSigStrength);
925 ts->ts_shortretry = MS(ads->ds_txstatus0, AR_RTSFailCnt);
926 ts->ts_longretry = MS(ads->ds_txstatus0, AR_DataFailCnt);
938 switch (ts->ts_finaltsi) {
939 case 3: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries2);
940 case 2: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries1);
941 case 1: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries0);
943 ts->ts_virtcol = MS(ads->ds_txstatus0, AR_VirtCollCnt);
944 ts->ts_antenna = (ads->ds_txstatus1 & AR_XmitAtenna ? 2 : 1);