ath_hal/ar5211/ar5211_xmit.c

118 	HAL_TX_QUEUE_INFO *qi;
141 	qi = &ahp->ah_txq[q];
142 	if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) {
147 	OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO));
148 	qi->tqi_type = type;
151 		qi->tqi_qflags =
157 		qi->tqi_aifs = INIT_AIFS;
158 		qi->tqi_cwmin = HAL_TXQ_USEDEFAULT;	/* NB: do at reset */
159 		qi->tqi_cwmax = INIT_CWMAX;
160 		qi->tqi_shretry = INIT_SH_RETRY;
161 		qi->tqi_lgretry = INIT_LG_RETRY;
171 setTxQInterrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)
203 	HAL_TX_QUEUE_INFO *qi;
210 	qi = &ahp->ah_txq[q];
211 	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
219 	qi->tqi_type = HAL_TX_QUEUE_INACTIVE;
225 	setTxQInterrupts(ah, qi);
238 	HAL_TX_QUEUE_INFO *qi;
246 	qi = &ahp->ah_txq[q];
247 	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
253 	if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) {
266 		cwMin = qi->tqi_cwmin;
271 		| SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
272 		| SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
278 		 | SM(qi->tqi_lgretry, AR_D_RETRY_LIMIT_FR_LG)
279 		 | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)
290 	if (qi->tqi_cbrPeriod) {
292 			  SM(qi->tqi_cbrPeriod,AR_Q_CBRCFG_CBR_INTERVAL)
293 			| SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_CBR_OVF_THRESH));
297 			(qi->tqi_cbrOverflowLimit ?
300 	if (qi->tqi_readyTime) {
302 			SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_INT) |
305 	if (qi->tqi_burstTime) {
307 			SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
309 		if (qi->tqi_qflags & HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE) {
316 	if (qi->tqi_qflags & HAL_TXQ_BACKOFF_DISABLE) {
321 	if (qi->tqi_qflags & HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE) {
326 	switch (qi->tqi_type) {
375 	if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE)
379 	if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE)
383 	if (qi->tqi_qflags & HAL_TXQ_TXDESCINT_ENABLE)
387 	if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE)
391 	if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE)
395 	setTxQInterrupts(ah, qi);