Lines Matching refs:u_int32_t
24 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
26 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
27 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
28 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
29 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
30 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
31 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
32 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
33 volatile u_int32_t MAC_DMA_TXCFG; /* 0x30 - 0x34 */
34 volatile u_int32_t MAC_DMA_RXCFG; /* 0x34 - 0x38 */
35 volatile u_int32_t MAC_DMA_RXJLA; /* 0x38 - 0x3c */
37 volatile u_int32_t MAC_DMA_MIBC; /* 0x40 - 0x44 */
38 volatile u_int32_t MAC_DMA_TOPS; /* 0x44 - 0x48 */
39 volatile u_int32_t MAC_DMA_RXNPTO; /* 0x48 - 0x4c */
40 volatile u_int32_t MAC_DMA_TXNPTO; /* 0x4c - 0x50 */
41 volatile u_int32_t MAC_DMA_RPGTO; /* 0x50 - 0x54 */
43 volatile u_int32_t MAC_DMA_MACMISC; /* 0x58 - 0x5c */
44 volatile u_int32_t MAC_DMA_INTER; /* 0x5c - 0x60 */
45 volatile u_int32_t MAC_DMA_DATABUF; /* 0x60 - 0x64 */
46 volatile u_int32_t MAC_DMA_GTT; /* 0x64 - 0x68 */
47 volatile u_int32_t MAC_DMA_GTTM; /* 0x68 - 0x6c */
48 volatile u_int32_t MAC_DMA_CST; /* 0x6c - 0x70 */
49 volatile u_int32_t MAC_DMA_RXDP_SIZE; /* 0x70 - 0x74 */
50 volatile u_int32_t MAC_DMA_RX_QUEUE_HP_RXDP; /* 0x74 - 0x78 */
51 volatile u_int32_t MAC_DMA_RX_QUEUE_LP_RXDP; /* 0x78 - 0x7c */
53 volatile u_int32_t MAC_DMA_ISR_P; /* 0x80 - 0x84 */
54 volatile u_int32_t MAC_DMA_ISR_S0; /* 0x84 - 0x88 */
55 volatile u_int32_t MAC_DMA_ISR_S1; /* 0x88 - 0x8c */
56 volatile u_int32_t MAC_DMA_ISR_S2; /* 0x8c - 0x90 */
57 volatile u_int32_t MAC_DMA_ISR_S3; /* 0x90 - 0x94 */
58 volatile u_int32_t MAC_DMA_ISR_S4; /* 0x94 - 0x98 */
59 volatile u_int32_t MAC_DMA_ISR_S5; /* 0x98 - 0x9c */
61 volatile u_int32_t MAC_DMA_IMR_P; /* 0xa0 - 0xa4 */
62 volatile u_int32_t MAC_DMA_IMR_S0; /* 0xa4 - 0xa8 */
63 volatile u_int32_t MAC_DMA_IMR_S1; /* 0xa8 - 0xac */
64 volatile u_int32_t MAC_DMA_IMR_S2; /* 0xac - 0xb0 */
65 volatile u_int32_t MAC_DMA_IMR_S3; /* 0xb0 - 0xb4 */
66 volatile u_int32_t MAC_DMA_IMR_S4; /* 0xb4 - 0xb8 */
67 volatile u_int32_t MAC_DMA_IMR_S5; /* 0xb8 - 0xbc */
69 volatile u_int32_t MAC_DMA_ISR_P_RAC; /* 0xc0 - 0xc4 */
70 volatile u_int32_t MAC_DMA_ISR_S0_S; /* 0xc4 - 0xc8 */
71 volatile u_int32_t MAC_DMA_ISR_S1_S; /* 0xc8 - 0xcc */
73 volatile u_int32_t MAC_DMA_ISR_S2_S; /* 0xd0 - 0xd4 */
74 volatile u_int32_t MAC_DMA_ISR_S3_S; /* 0xd4 - 0xd8 */
75 volatile u_int32_t MAC_DMA_ISR_S4_S; /* 0xd8 - 0xdc */
76 volatile u_int32_t MAC_DMA_ISR_S5_S; /* 0xdc - 0xe0 */
77 volatile u_int32_t MAC_DMA_DMADBG_0; /* 0xe0 - 0xe4 */
78 volatile u_int32_t MAC_DMA_DMADBG_1; /* 0xe4 - 0xe8 */
79 volatile u_int32_t MAC_DMA_DMADBG_2; /* 0xe8 - 0xec */
80 volatile u_int32_t MAC_DMA_DMADBG_3; /* 0xec - 0xf0 */
81 volatile u_int32_t MAC_DMA_DMADBG_4; /* 0xf0 - 0xf4 */
82 volatile u_int32_t MAC_DMA_DMADBG_5; /* 0xf4 - 0xf8 */
83 volatile u_int32_t MAC_DMA_DMADBG_6; /* 0xf8 - 0xfc */
84 volatile u_int32_t MAC_DMA_DMADBG_7; /* 0xfc - 0x100 */
85 volatile u_int32_t MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0;
87 volatile u_int32_t MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8;
89 volatile u_int32_t MAC_DMA_TIMT_0; /* 0x108 - 0x10c */
90 volatile u_int32_t MAC_DMA_TIMT_1; /* 0x10c - 0x110 */
91 volatile u_int32_t MAC_DMA_TIMT_2; /* 0x110 - 0x114 */
92 volatile u_int32_t MAC_DMA_TIMT_3; /* 0x114 - 0x118 */
93 volatile u_int32_t MAC_DMA_TIMT_4; /* 0x118 - 0x11c */
94 volatile u_int32_t MAC_DMA_TIMT_5; /* 0x11c - 0x120 */
95 volatile u_int32_t MAC_DMA_TIMT_6; /* 0x120 - 0x124 */
96 volatile u_int32_t MAC_DMA_TIMT_7; /* 0x124 - 0x128 */
97 volatile u_int32_t MAC_DMA_TIMT_8; /* 0x128 - 0x12c */
98 volatile u_int32_t MAC_DMA_TIMT_9; /* 0x12c - 0x130 */
102 volatile u_int32_t MAC_QCU_TXDP[10]; /* 0x0 - 0x28 */
104 volatile u_int32_t MAC_QCU_STATUS_RING_START; /* 0x30 - 0x34 */
105 volatile u_int32_t MAC_QCU_STATUS_RING_END; /* 0x34 - 0x38 */
106 volatile u_int32_t MAC_QCU_STATUS_RING_CURRENT; /* 0x38 - 0x3c */
108 volatile u_int32_t MAC_QCU_TXE; /* 0x40 - 0x44 */
110 volatile u_int32_t MAC_QCU_TXD; /* 0x80 - 0x84 */
112 volatile u_int32_t MAC_QCU_CBR[10]; /* 0xc0 - 0xe8 */
114 volatile u_int32_t MAC_QCU_RDYTIME[10]; /* 0x100 - 0x128 */
116 volatile u_int32_t MAC_QCU_ONESHOT_ARM_SC; /* 0x140 - 0x144 */
118 volatile u_int32_t MAC_QCU_ONESHOT_ARM_CC; /* 0x180 - 0x184 */
120 volatile u_int32_t MAC_QCU_MISC[10]; /* 0x1c0 - 0x1e8 */
122 volatile u_int32_t MAC_QCU_CNT[10]; /* 0x200 - 0x228 */
124 volatile u_int32_t MAC_QCU_RDYTIME_SHDN; /* 0x240 - 0x244 */
125 volatile u_int32_t MAC_QCU_DESC_CRC_CHK; /* 0x244 - 0x248 */
129 volatile u_int32_t MAC_DCU_QCUMASK[10]; /* 0x0 - 0x28 */
131 volatile u_int32_t MAC_DCU_GBL_IFS_SIFS; /* 0x30 - 0x34 */
133 volatile u_int32_t MAC_DCU_TXFILTER_DCU0_31_0; /* 0x38 - 0x3c */
134 volatile u_int32_t MAC_DCU_TXFILTER_DCU8_31_0; /* 0x3c - 0x40 */
135 volatile u_int32_t MAC_DCU_LCL_IFS[10]; /* 0x40 - 0x68 */
137 volatile u_int32_t MAC_DCU_GBL_IFS_SLOT; /* 0x70 - 0x74 */
139 volatile u_int32_t MAC_DCU_TXFILTER_DCU0_63_32; /* 0x78 - 0x7c */
140 volatile u_int32_t MAC_DCU_TXFILTER_DCU8_63_32; /* 0x7c - 0x80 */
141 volatile u_int32_t MAC_DCU_RETRY_LIMIT[10]; /* 0x80 - 0xa8 */
143 volatile u_int32_t MAC_DCU_GBL_IFS_EIFS; /* 0xb0 - 0xb4 */
145 volatile u_int32_t MAC_DCU_TXFILTER_DCU0_95_64; /* 0xb8 - 0xbc */
146 volatile u_int32_t MAC_DCU_TXFILTER_DCU8_95_64; /* 0xbc - 0xc0 */
147 volatile u_int32_t MAC_DCU_CHANNEL_TIME[10]; /* 0xc0 - 0xe8 */
149 volatile u_int32_t MAC_DCU_GBL_IFS_MISC; /* 0xf0 - 0xf4 */
151 volatile u_int32_t MAC_DCU_TXFILTER_DCU0_127_96;
153 volatile u_int32_t MAC_DCU_TXFILTER_DCU8_127_96;
155 volatile u_int32_t MAC_DCU_MISC[10]; /* 0x100 - 0x128 */
157 volatile u_int32_t MAC_DCU_TXFILTER_DCU1_31_0; /* 0x138 - 0x13c */
158 volatile u_int32_t MAC_DCU_TXFILTER_DCU9_31_0; /* 0x13c - 0x140 */
159 volatile u_int32_t MAC_DCU_SEQ; /* 0x140 - 0x144 */
161 volatile u_int32_t MAC_DCU_TXFILTER_DCU1_63_32; /* 0x178 - 0x17c */
162 volatile u_int32_t MAC_DCU_TXFILTER_DCU9_63_32; /* 0x17c - 0x180 */
164 volatile u_int32_t MAC_DCU_TXFILTER_DCU1_95_64; /* 0x1b8 - 0x1bc */
165 volatile u_int32_t MAC_DCU_TXFILTER_DCU9_95_64; /* 0x1bc - 0x1c0 */
167 volatile u_int32_t MAC_DCU_TXFILTER_DCU1_127_96;
169 volatile u_int32_t MAC_DCU_TXFILTER_DCU9_127_96;
172 volatile u_int32_t MAC_DCU_TXFILTER_DCU2_31_0; /* 0x238 - 0x23c */
174 volatile u_int32_t MAC_DCU_PAUSE; /* 0x270 - 0x274 */
176 volatile u_int32_t MAC_DCU_TXFILTER_DCU2_63_32; /* 0x278 - 0x27c */
178 volatile u_int32_t MAC_DCU_WOW_KACFG; /* 0x2b0 - 0x2b4 */
180 volatile u_int32_t MAC_DCU_TXFILTER_DCU2_95_64; /* 0x2b8 - 0x2bc */
182 volatile u_int32_t MAC_DCU_TXSLOT; /* 0x2f0 - 0x2f4 */
184 volatile u_int32_t MAC_DCU_TXFILTER_DCU2_127_96;
187 volatile u_int32_t MAC_DCU_TXFILTER_DCU3_31_0; /* 0x338 - 0x33c */
189 volatile u_int32_t MAC_DCU_TXFILTER_DCU3_63_32; /* 0x378 - 0x37c */
191 volatile u_int32_t MAC_DCU_TXFILTER_DCU3_95_64; /* 0x3b8 - 0x3bc */
193 volatile u_int32_t MAC_DCU_TXFILTER_DCU3_127_96;
196 volatile u_int32_t MAC_DCU_TXFILTER_DCU4_31_0; /* 0x438 - 0x43c */
197 volatile u_int32_t MAC_DCU_TXFILTER_CLEAR; /* 0x43c - 0x440 */
199 volatile u_int32_t MAC_DCU_TXFILTER_DCU4_63_32; /* 0x478 - 0x47c */
200 volatile u_int32_t MAC_DCU_TXFILTER_SET; /* 0x47c - 0x480 */
202 volatile u_int32_t MAC_DCU_TXFILTER_DCU4_95_64; /* 0x4b8 - 0x4bc */
204 volatile u_int32_t MAC_DCU_TXFILTER_DCU4_127_96;
207 volatile u_int32_t MAC_DCU_TXFILTER_DCU5_31_0; /* 0x538 - 0x53c */
209 volatile u_int32_t MAC_DCU_TXFILTER_DCU5_63_32; /* 0x578 - 0x57c */
211 volatile u_int32_t MAC_DCU_TXFILTER_DCU5_95_64; /* 0x5b8 - 0x5bc */
213 volatile u_int32_t MAC_DCU_TXFILTER_DCU5_127_96;
216 volatile u_int32_t MAC_DCU_TXFILTER_DCU6_31_0; /* 0x638 - 0x63c */
218 volatile u_int32_t MAC_DCU_TXFILTER_DCU6_63_32; /* 0x678 - 0x67c */
220 volatile u_int32_t MAC_DCU_TXFILTER_DCU6_95_64; /* 0x6b8 - 0x6bc */
222 volatile u_int32_t MAC_DCU_TXFILTER_DCU6_127_96;
225 volatile u_int32_t MAC_DCU_TXFILTER_DCU7_31_0; /* 0x738 - 0x73c */
227 volatile u_int32_t MAC_DCU_TXFILTER_DCU7_63_32; /* 0x778 - 0x77c */
229 volatile u_int32_t MAC_DCU_TXFILTER_DCU7_95_64; /* 0x7b8 - 0x7bc */
231 volatile u_int32_t MAC_DCU_TXFILTER_DCU7_127_96;
234 volatile u_int32_t MAC_SLEEP_STATUS; /* 0xf00 - 0xf04 */
235 volatile u_int32_t MAC_LED_CONFIG; /* 0xf04 - 0xf08 */
239 volatile u_int32_t RESET_CONTROL; /* 0x0 - 0x4 */
240 volatile u_int32_t XTAL_CONTROL; /* 0x4 - 0x8 */
241 volatile u_int32_t REG_CONTROL0; /* 0x8 - 0xc */
242 volatile u_int32_t REG_CONTROL1; /* 0xc - 0x10 */
243 volatile u_int32_t QUADRATURE; /* 0x10 - 0x14 */
244 volatile u_int32_t PLL_CONTROL; /* 0x14 - 0x18 */
245 volatile u_int32_t PLL_SETTLE; /* 0x18 - 0x1c */
246 volatile u_int32_t XTAL_SETTLE; /* 0x1c - 0x20 */
247 volatile u_int32_t CLOCK_OUT; /* 0x20 - 0x24 */
248 volatile u_int32_t BIAS_OVERRIDE; /* 0x24 - 0x28 */
249 volatile u_int32_t RESET_CAUSE; /* 0x28 - 0x2c */
250 volatile u_int32_t SYSTEM_SLEEP; /* 0x2c - 0x30 */
251 volatile u_int32_t MAC_SLEEP_CONTROL; /* 0x30 - 0x34 */
252 volatile u_int32_t KEEP_AWAKE; /* 0x34 - 0x38 */
253 volatile u_int32_t DERIVED_RTC_CLK; /* 0x38 - 0x3c */
254 volatile u_int32_t PLL_CONTROL2; /* 0x3c - 0x40 */
258 volatile u_int32_t RTC_SYNC_RESET; /* 0x0 - 0x4 */
259 volatile u_int32_t RTC_SYNC_STATUS; /* 0x4 - 0x8 */
260 volatile u_int32_t RTC_SYNC_DERIVED; /* 0x8 - 0xc */
261 volatile u_int32_t RTC_SYNC_FORCE_WAKE; /* 0xc - 0x10 */
262 volatile u_int32_t RTC_SYNC_INTR_CAUSE; /* 0x10 - 0x14 */
263 volatile u_int32_t RTC_SYNC_INTR_ENABLE; /* 0x14 - 0x18 */
264 volatile u_int32_t RTC_SYNC_INTR_MASK; /* 0x18 - 0x1c */
268 volatile u_int32_t MAC_PCU_STA_ADDR_L32; /* 0x0 - 0x4 */
269 volatile u_int32_t MAC_PCU_STA_ADDR_U16; /* 0x4 - 0x8 */
270 volatile u_int32_t MAC_PCU_BSSID_L32; /* 0x8 - 0xc */
271 volatile u_int32_t MAC_PCU_BSSID_U16; /* 0xc - 0x10 */
272 volatile u_int32_t MAC_PCU_BCN_RSSI_AVE; /* 0x10 - 0x14 */
273 volatile u_int32_t MAC_PCU_ACK_CTS_TIMEOUT; /* 0x14 - 0x18 */
274 volatile u_int32_t MAC_PCU_BCN_RSSI_CTL; /* 0x18 - 0x1c */
275 volatile u_int32_t MAC_PCU_USEC_LATENCY; /* 0x1c - 0x20 */
276 volatile u_int32_t MAC_PCU_RESET_TSF; /* 0x20 - 0x24 */
278 volatile u_int32_t MAC_PCU_MAX_CFP_DUR; /* 0x38 - 0x3c */
279 volatile u_int32_t MAC_PCU_RX_FILTER; /* 0x3c - 0x40 */
280 volatile u_int32_t MAC_PCU_MCAST_FILTER_L32; /* 0x40 - 0x44 */
281 volatile u_int32_t MAC_PCU_MCAST_FILTER_U32; /* 0x44 - 0x48 */
282 volatile u_int32_t MAC_PCU_DIAG_SW; /* 0x48 - 0x4c */
283 volatile u_int32_t MAC_PCU_TSF_L32; /* 0x4c - 0x50 */
284 volatile u_int32_t MAC_PCU_TSF_U32; /* 0x50 - 0x54 */
285 volatile u_int32_t MAC_PCU_TST_ADDAC; /* 0x54 - 0x58 */
286 volatile u_int32_t MAC_PCU_DEF_ANTENNA; /* 0x58 - 0x5c */
287 volatile u_int32_t MAC_PCU_AES_MUTE_MASK_0; /* 0x5c - 0x60 */
288 volatile u_int32_t MAC_PCU_AES_MUTE_MASK_1; /* 0x60 - 0x64 */
289 volatile u_int32_t MAC_PCU_GATED_CLKS; /* 0x64 - 0x68 */
290 volatile u_int32_t MAC_PCU_OBS_BUS_2; /* 0x68 - 0x6c */
291 volatile u_int32_t MAC_PCU_OBS_BUS_1; /* 0x6c - 0x70 */
292 volatile u_int32_t MAC_PCU_DYM_MIMO_PWR_SAVE; /* 0x70 - 0x74 */
293 volatile u_int32_t MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB;
295 volatile u_int32_t MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB;
298 volatile u_int32_t MAC_PCU_LAST_BEACON_TSF; /* 0x80 - 0x84 */
299 volatile u_int32_t MAC_PCU_NAV; /* 0x84 - 0x88 */
300 volatile u_int32_t MAC_PCU_RTS_SUCCESS_CNT; /* 0x88 - 0x8c */
301 volatile u_int32_t MAC_PCU_RTS_FAIL_CNT; /* 0x8c - 0x90 */
302 volatile u_int32_t MAC_PCU_ACK_FAIL_CNT; /* 0x90 - 0x94 */
303 volatile u_int32_t MAC_PCU_FCS_FAIL_CNT; /* 0x94 - 0x98 */
304 volatile u_int32_t MAC_PCU_BEACON_CNT; /* 0x98 - 0x9c */
305 volatile u_int32_t MAC_PCU_TDMA_SLOT_ALERT_CNTL;
307 volatile u_int32_t MAC_PCU_BASIC_SET; /* 0xa0 - 0xa4 */
308 volatile u_int32_t MAC_PCU_MGMT_SEQ; /* 0xa4 - 0xa8 */
309 volatile u_int32_t MAC_PCU_BF_RPT1; /* 0xa8 - 0xac */
310 volatile u_int32_t MAC_PCU_BF_RPT2; /* 0xac - 0xb0 */
311 volatile u_int32_t MAC_PCU_TX_ANT_1; /* 0xb0 - 0xb4 */
312 volatile u_int32_t MAC_PCU_TX_ANT_2; /* 0xb4 - 0xb8 */
313 volatile u_int32_t MAC_PCU_TX_ANT_3; /* 0xb8 - 0xbc */
314 volatile u_int32_t MAC_PCU_TX_ANT_4; /* 0xbc - 0xc0 */
315 volatile u_int32_t MAC_PCU_XRMODE; /* 0xc0 - 0xc4 */
316 volatile u_int32_t MAC_PCU_XRDEL; /* 0xc4 - 0xc8 */
317 volatile u_int32_t MAC_PCU_XRTO; /* 0xc8 - 0xcc */
318 volatile u_int32_t MAC_PCU_XRCRP; /* 0xcc - 0xd0 */
319 volatile u_int32_t MAC_PCU_XRSTMP; /* 0xd0 - 0xd4 */
320 volatile u_int32_t MAC_PCU_SLP1; /* 0xd4 - 0xd8 */
321 volatile u_int32_t MAC_PCU_SLP2; /* 0xd8 - 0xdc */
322 volatile u_int32_t MAC_PCU_SELF_GEN_DEFAULT; /* 0xdc - 0xe0 */
323 volatile u_int32_t MAC_PCU_ADDR1_MASK_L32; /* 0xe0 - 0xe4 */
324 volatile u_int32_t MAC_PCU_ADDR1_MASK_U16; /* 0xe4 - 0xe8 */
325 volatile u_int32_t MAC_PCU_TPC; /* 0xe8 - 0xec */
326 volatile u_int32_t MAC_PCU_TX_FRAME_CNT; /* 0xec - 0xf0 */
327 volatile u_int32_t MAC_PCU_RX_FRAME_CNT; /* 0xf0 - 0xf4 */
328 volatile u_int32_t MAC_PCU_RX_CLEAR_CNT; /* 0xf4 - 0xf8 */
329 volatile u_int32_t MAC_PCU_CYCLE_CNT; /* 0xf8 - 0xfc */
330 volatile u_int32_t MAC_PCU_QUIET_TIME_1; /* 0xfc - 0x100 */
331 volatile u_int32_t MAC_PCU_QUIET_TIME_2; /* 0x100 - 0x104 */
333 volatile u_int32_t MAC_PCU_QOS_NO_ACK; /* 0x108 - 0x10c */
334 volatile u_int32_t MAC_PCU_PHY_ERROR_MASK; /* 0x10c - 0x110 */
335 volatile u_int32_t MAC_PCU_XRLAT; /* 0x110 - 0x114 */
336 volatile u_int32_t MAC_PCU_RXBUF; /* 0x114 - 0x118 */
337 volatile u_int32_t MAC_PCU_MIC_QOS_CONTROL; /* 0x118 - 0x11c */
338 volatile u_int32_t MAC_PCU_MIC_QOS_SELECT; /* 0x11c - 0x120 */
339 volatile u_int32_t MAC_PCU_MISC_MODE; /* 0x120 - 0x124 */
340 volatile u_int32_t MAC_PCU_FILTER_OFDM_CNT; /* 0x124 - 0x128 */
341 volatile u_int32_t MAC_PCU_FILTER_CCK_CNT; /* 0x128 - 0x12c */
342 volatile u_int32_t MAC_PCU_PHY_ERR_CNT_1; /* 0x12c - 0x130 */
343 volatile u_int32_t MAC_PCU_PHY_ERR_CNT_1_MASK; /* 0x130 - 0x134 */
344 volatile u_int32_t MAC_PCU_PHY_ERR_CNT_2; /* 0x134 - 0x138 */
345 volatile u_int32_t MAC_PCU_PHY_ERR_CNT_2_MASK; /* 0x138 - 0x13c */
346 volatile u_int32_t MAC_PCU_TSF_THRESHOLD; /* 0x13c - 0x140 */
347 volatile u_int32_t MAC_PCU_MISC_MODE4; /* 0x140 - 0x144 */
348 volatile u_int32_t MAC_PCU_PHY_ERROR_EIFS_MASK; /* 0x144 - 0x148 */
350 volatile u_int32_t MAC_PCU_PHY_ERR_CNT_3; /* 0x168 - 0x16c */
351 volatile u_int32_t MAC_PCU_PHY_ERR_CNT_3_MASK; /* 0x16c - 0x170 */
352 volatile u_int32_t MAC_PCU_BLUETOOTH_MODE; /* 0x170 - 0x174 */
353 volatile u_int32_t MAC_PCU_BLUETOOTH_WL_WEIGHTS0;
355 volatile u_int32_t MAC_PCU_HCF_TIMEOUT; /* 0x178 - 0x17c */
356 volatile u_int32_t MAC_PCU_BLUETOOTH_MODE2; /* 0x17c - 0x180 */
357 volatile u_int32_t MAC_PCU_GENERIC_TIMERS2[16]; /* 0x180 - 0x1c0 */
358 volatile u_int32_t MAC_PCU_GENERIC_TIMERS2_MODE;
360 volatile u_int32_t MAC_PCU_BLUETOOTH_WL_WEIGHTS1;
362 volatile u_int32_t MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE;
364 volatile u_int32_t MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY;
366 volatile u_int32_t MAC_PCU_TXSIFS; /* 0x1d0 - 0x1d4 */
367 volatile u_int32_t MAC_PCU_BLUETOOTH_MODE3; /* 0x1d4 - 0x1d8 */
369 volatile u_int32_t MAC_PCU_TXOP_X; /* 0x1ec - 0x1f0 */
370 volatile u_int32_t MAC_PCU_TXOP_0_3; /* 0x1f0 - 0x1f4 */
371 volatile u_int32_t MAC_PCU_TXOP_4_7; /* 0x1f4 - 0x1f8 */
372 volatile u_int32_t MAC_PCU_TXOP_8_11; /* 0x1f8 - 0x1fc */
373 volatile u_int32_t MAC_PCU_TXOP_12_15; /* 0x1fc - 0x200 */
374 volatile u_int32_t MAC_PCU_GENERIC_TIMERS[16]; /* 0x200 - 0x240 */
375 volatile u_int32_t MAC_PCU_GENERIC_TIMERS_MODE; /* 0x240 - 0x244 */
376 volatile u_int32_t MAC_PCU_SLP32_MODE; /* 0x244 - 0x248 */
377 volatile u_int32_t MAC_PCU_SLP32_WAKE; /* 0x248 - 0x24c */
378 volatile u_int32_t MAC_PCU_SLP32_INC; /* 0x24c - 0x250 */
379 volatile u_int32_t MAC_PCU_SLP_MIB1; /* 0x250 - 0x254 */
380 volatile u_int32_t MAC_PCU_SLP_MIB2; /* 0x254 - 0x258 */
381 volatile u_int32_t MAC_PCU_SLP_MIB3; /* 0x258 - 0x25c */
382 volatile u_int32_t MAC_PCU_WOW1; /* 0x25c - 0x260 */
383 volatile u_int32_t MAC_PCU_WOW2; /* 0x260 - 0x264 */
384 volatile u_int32_t MAC_PCU_LOGIC_ANALYZER; /* 0x264 - 0x268 */
385 volatile u_int32_t MAC_PCU_LOGIC_ANALYZER_32L; /* 0x268 - 0x26c */
386 volatile u_int32_t MAC_PCU_LOGIC_ANALYZER_16U; /* 0x26c - 0x270 */
387 volatile u_int32_t MAC_PCU_WOW3_BEACON_FAIL; /* 0x270 - 0x274 */
388 volatile u_int32_t MAC_PCU_WOW3_BEACON; /* 0x274 - 0x278 */
389 volatile u_int32_t MAC_PCU_WOW3_KEEP_ALIVE; /* 0x278 - 0x27c */
390 volatile u_int32_t MAC_PCU_WOW_KA; /* 0x27c - 0x280 */
392 volatile u_int32_t PCU_1US; /* 0x284 - 0x288 */
393 volatile u_int32_t PCU_KA; /* 0x288 - 0x28c */
394 volatile u_int32_t WOW_EXACT; /* 0x28c - 0x290 */
396 volatile u_int32_t PCU_WOW4; /* 0x294 - 0x298 */
397 volatile u_int32_t PCU_WOW5; /* 0x298 - 0x29c */
398 volatile u_int32_t MAC_PCU_PHY_ERR_CNT_MASK_CONT;
401 volatile u_int32_t MAC_PCU_AZIMUTH_MODE; /* 0x300 - 0x304 */
403 volatile u_int32_t MAC_PCU_AZIMUTH_TIME_STAMP; /* 0x314 - 0x318 */
404 volatile u_int32_t MAC_PCU_20_40_MODE; /* 0x318 - 0x31c */
405 volatile u_int32_t MAC_PCU_H_XFER_TIMEOUT; /* 0x31c - 0x320 */
407 volatile u_int32_t MAC_PCU_RX_CLEAR_DIFF_CNT; /* 0x328 - 0x32c */
408 volatile u_int32_t MAC_PCU_SELF_GEN_ANTENNA_MASK;
410 volatile u_int32_t MAC_PCU_BA_BAR_CONTROL; /* 0x330 - 0x334 */
411 volatile u_int32_t MAC_PCU_LEGACY_PLCP_SPOOF; /* 0x334 - 0x338 */
412 volatile u_int32_t MAC_PCU_PHY_ERROR_MASK_CONT; /* 0x338 - 0x33c */
413 volatile u_int32_t MAC_PCU_TX_TIMER; /* 0x33c - 0x340 */
414 volatile u_int32_t MAC_PCU_TXBUF_CTRL; /* 0x340 - 0x344 */
415 volatile u_int32_t MAC_PCU_MISC_MODE2; /* 0x344 - 0x348 */
416 volatile u_int32_t MAC_PCU_ALT_AES_MUTE_MASK; /* 0x348 - 0x34c */
417 volatile u_int32_t MAC_PCU_WOW6; /* 0x34c - 0x350 */
418 volatile u_int32_t ASYNC_FIFO_REG1; /* 0x350 - 0x354 */
419 volatile u_int32_t ASYNC_FIFO_REG2; /* 0x354 - 0x358 */
420 volatile u_int32_t ASYNC_FIFO_REG3; /* 0x358 - 0x35c */
421 volatile u_int32_t MAC_PCU_WOW5; /* 0x35c - 0x360 */
422 volatile u_int32_t MAC_PCU_WOW_LENGTH1; /* 0x360 - 0x364 */
423 volatile u_int32_t MAC_PCU_WOW_LENGTH2; /* 0x364 - 0x368 */
424 volatile u_int32_t WOW_PATTERN_MATCH_LESS_THAN_256_BYTES;
427 volatile u_int32_t MAC_PCU_WOW4; /* 0x370 - 0x374 */
428 volatile u_int32_t WOW2_EXACT; /* 0x374 - 0x378 */
429 volatile u_int32_t PCU_WOW6; /* 0x378 - 0x37c */
430 volatile u_int32_t PCU_WOW7; /* 0x37c - 0x380 */
431 volatile u_int32_t MAC_PCU_WOW_LENGTH3; /* 0x380 - 0x384 */
432 volatile u_int32_t MAC_PCU_WOW_LENGTH4; /* 0x384 - 0x388 */
433 volatile u_int32_t MAC_PCU_LOCATION_MODE_CONTROL;
435 volatile u_int32_t MAC_PCU_LOCATION_MODE_TIMER; /* 0x38c - 0x390 */
436 volatile u_int32_t MAC_PCU_TSF2_L32; /* 0x390 - 0x394 */
437 volatile u_int32_t MAC_PCU_TSF2_U32; /* 0x394 - 0x398 */
438 volatile u_int32_t MAC_PCU_BSSID2_L32; /* 0x398 - 0x39c */
439 volatile u_int32_t MAC_PCU_BSSID2_U16; /* 0x39c - 0x3a0 */
440 volatile u_int32_t MAC_PCU_DIRECT_CONNECT; /* 0x3a0 - 0x3a4 */
441 volatile u_int32_t MAC_PCU_TID_TO_AC; /* 0x3a4 - 0x3a8 */
442 volatile u_int32_t MAC_PCU_HP_QUEUE; /* 0x3a8 - 0x3ac */
443 volatile u_int32_t MAC_PCU_BLUETOOTH_BT_WEIGHTS0;
445 volatile u_int32_t MAC_PCU_BLUETOOTH_BT_WEIGHTS1;
447 volatile u_int32_t MAC_PCU_BLUETOOTH_BT_WEIGHTS2;
449 volatile u_int32_t MAC_PCU_BLUETOOTH_BT_WEIGHTS3;
451 volatile u_int32_t MAC_PCU_AGC_SATURATION_CNT0; /* 0x3bc - 0x3c0 */
452 volatile u_int32_t MAC_PCU_AGC_SATURATION_CNT1; /* 0x3c0 - 0x3c4 */
453 volatile u_int32_t MAC_PCU_AGC_SATURATION_CNT2; /* 0x3c4 - 0x3c8 */
454 volatile u_int32_t MAC_PCU_HW_BCN_PROC1; /* 0x3c8 - 0x3cc */
455 volatile u_int32_t MAC_PCU_HW_BCN_PROC2; /* 0x3cc - 0x3d0 */
456 volatile u_int32_t MAC_PCU_MISC_MODE3; /* 0x3d0 - 0x3d4 */
457 volatile u_int32_t MAC_PCU_FILTER_RSSI_AVE; /* 0x3d4 - 0x3d8 */
458 volatile u_int32_t MAC_PCU_PHY_ERROR_AIFS_MASK; /* 0x3d8 - 0x3dc */
459 volatile u_int32_t MAC_PCU_PS_FILTER; /* 0x3dc - 0x3e0 */
461 volatile u_int32_t MAC_PCU_TXBUF_BA[64]; /* 0x400 - 0x500 */
463 volatile u_int32_t MAC_PCU_KEY_CACHE[1024]; /* 0x800 - 0x1800 */
467 volatile u_int32_t BB_timing_controls_1; /* 0x0 - 0x4 */
468 volatile u_int32_t BB_timing_controls_2; /* 0x4 - 0x8 */
469 volatile u_int32_t BB_timing_controls_3; /* 0x8 - 0xc */
470 volatile u_int32_t BB_timing_control_4; /* 0xc - 0x10 */
471 volatile u_int32_t BB_timing_control_5; /* 0x10 - 0x14 */
472 volatile u_int32_t BB_timing_control_6; /* 0x14 - 0x18 */
473 volatile u_int32_t BB_timing_control_11; /* 0x18 - 0x1c */
474 volatile u_int32_t BB_spur_mask_controls; /* 0x1c - 0x20 */
475 volatile u_int32_t BB_find_signal_low; /* 0x20 - 0x24 */
476 volatile u_int32_t BB_sfcorr; /* 0x24 - 0x28 */
477 volatile u_int32_t BB_self_corr_low; /* 0x28 - 0x2c */
478 volatile u_int32_t BB_ext_chan_scorr_thr; /* 0x2c - 0x30 */
479 volatile u_int32_t BB_ext_chan_pwr_thr_2_b0; /* 0x30 - 0x34 */
480 volatile u_int32_t BB_radar_detection; /* 0x34 - 0x38 */
481 volatile u_int32_t BB_radar_detection_2; /* 0x38 - 0x3c */
482 volatile u_int32_t BB_extension_radar; /* 0x3c - 0x40 */
484 volatile u_int32_t BB_multichain_control; /* 0x80 - 0x84 */
485 volatile u_int32_t BB_per_chain_csd; /* 0x84 - 0x88 */
487 volatile u_int32_t BB_tx_crc; /* 0xa0 - 0xa4 */
488 volatile u_int32_t BB_tstdac_constant; /* 0xa4 - 0xa8 */
489 volatile u_int32_t BB_spur_report_b0; /* 0xa8 - 0xac */
491 volatile u_int32_t BB_txiqcal_control_3; /* 0xb0 - 0xb4 */
493 volatile u_int32_t BB_green_tx_control_1; /* 0xbc - 0xc0 */
494 volatile u_int32_t BB_iq_adc_meas_0_b0; /* 0xc0 - 0xc4 */
495 volatile u_int32_t BB_iq_adc_meas_1_b0; /* 0xc4 - 0xc8 */
496 volatile u_int32_t BB_iq_adc_meas_2_b0; /* 0xc8 - 0xcc */
497 volatile u_int32_t BB_iq_adc_meas_3_b0; /* 0xcc - 0xd0 */
498 volatile u_int32_t BB_tx_phase_ramp_b0; /* 0xd0 - 0xd4 */
499 volatile u_int32_t BB_adc_gain_dc_corr_b0; /* 0xd4 - 0xd8 */
501 volatile u_int32_t BB_rx_iq_corr_b0; /* 0xdc - 0xe0 */
503 volatile u_int32_t BB_paprd_am2am_mask; /* 0xe4 - 0xe8 */
504 volatile u_int32_t BB_paprd_am2pm_mask; /* 0xe8 - 0xec */
505 volatile u_int32_t BB_paprd_ht40_mask; /* 0xec - 0xf0 */
506 volatile u_int32_t BB_paprd_ctrl0_b0; /* 0xf0 - 0xf4 */
507 volatile u_int32_t BB_paprd_ctrl1_b0; /* 0xf4 - 0xf8 */
508 volatile u_int32_t BB_pa_gain123_b0; /* 0xf8 - 0xfc */
509 volatile u_int32_t BB_pa_gain45_b0; /* 0xfc - 0x100 */
510 volatile u_int32_t BB_paprd_pre_post_scale_0_b0;
512 volatile u_int32_t BB_paprd_pre_post_scale_1_b0;
514 volatile u_int32_t BB_paprd_pre_post_scale_2_b0;
516 volatile u_int32_t BB_paprd_pre_post_scale_3_b0;
518 volatile u_int32_t BB_paprd_pre_post_scale_4_b0;
520 volatile u_int32_t BB_paprd_pre_post_scale_5_b0;
522 volatile u_int32_t BB_paprd_pre_post_scale_6_b0;
524 volatile u_int32_t BB_paprd_pre_post_scale_7_b0;
526 volatile u_int32_t BB_paprd_mem_tab_b0[120]; /* 0x120 - 0x300 */
527 volatile u_int32_t BB_chan_info_chan_tab_b0[60];
529 volatile u_int32_t BB_chn_tables_intf_addr; /* 0x3f0 - 0x3f4 */
530 volatile u_int32_t BB_chn_tables_intf_data; /* 0x3f4 - 0x3f8 */
534 volatile u_int32_t BB_timing_control_3a; /* 0x0 - 0x4 */
535 volatile u_int32_t BB_ldpc_cntl1; /* 0x4 - 0x8 */
536 volatile u_int32_t BB_ldpc_cntl2; /* 0x8 - 0xc */
537 volatile u_int32_t BB_pilot_spur_mask; /* 0xc - 0x10 */
538 volatile u_int32_t BB_chan_spur_mask; /* 0x10 - 0x14 */
539 volatile u_int32_t BB_short_gi_delta_slope; /* 0x14 - 0x18 */
540 volatile u_int32_t BB_ml_cntl1; /* 0x18 - 0x1c */
541 volatile u_int32_t BB_ml_cntl2; /* 0x1c - 0x20 */
542 volatile u_int32_t BB_tstadc; /* 0x20 - 0x24 */
546 volatile u_int32_t BB_bbb_rx_ctrl_1; /* 0x0 - 0x4 */
547 volatile u_int32_t BB_bbb_rx_ctrl_2; /* 0x4 - 0x8 */
548 volatile u_int32_t BB_bbb_rx_ctrl_3; /* 0x8 - 0xc */
549 volatile u_int32_t BB_bbb_rx_ctrl_4; /* 0xc - 0x10 */
550 volatile u_int32_t BB_bbb_rx_ctrl_5; /* 0x10 - 0x14 */
551 volatile u_int32_t BB_bbb_rx_ctrl_6; /* 0x14 - 0x18 */
552 volatile u_int32_t BB_force_clken_cck; /* 0x18 - 0x1c */
556 volatile u_int32_t BB_settling_time; /* 0x0 - 0x4 */
557 volatile u_int32_t BB_gain_force_max_gains_b0; /* 0x4 - 0x8 */
558 volatile u_int32_t BB_gains_min_offsets; /* 0x8 - 0xc */
559 volatile u_int32_t BB_desired_sigsize; /* 0xc - 0x10 */
560 volatile u_int32_t BB_find_signal; /* 0x10 - 0x14 */
561 volatile u_int32_t BB_agc; /* 0x14 - 0x18 */
562 volatile u_int32_t BB_ext_atten_switch_ctl_b0; /* 0x18 - 0x1c */
563 volatile u_int32_t BB_cca_b0; /* 0x1c - 0x20 */
564 volatile u_int32_t BB_cca_ctrl_2_b0; /* 0x20 - 0x24 */
565 volatile u_int32_t BB_restart; /* 0x24 - 0x28 */
566 volatile u_int32_t BB_multichain_gain_ctrl; /* 0x28 - 0x2c */
567 volatile u_int32_t BB_ext_chan_pwr_thr_1; /* 0x2c - 0x30 */
568 volatile u_int32_t BB_ext_chan_detect_win; /* 0x30 - 0x34 */
569 volatile u_int32_t BB_pwr_thr_20_40_det; /* 0x34 - 0x38 */
570 volatile u_int32_t BB_rifs_srch; /* 0x38 - 0x3c */
571 volatile u_int32_t BB_peak_det_ctrl_1; /* 0x3c - 0x40 */
572 volatile u_int32_t BB_peak_det_ctrl_2; /* 0x40 - 0x44 */
573 volatile u_int32_t BB_rx_gain_bounds_1; /* 0x44 - 0x48 */
574 volatile u_int32_t BB_rx_gain_bounds_2; /* 0x48 - 0x4c */
575 volatile u_int32_t BB_peak_det_cal_ctrl; /* 0x4c - 0x50 */
576 volatile u_int32_t BB_agc_dig_dc_ctrl; /* 0x50 - 0x54 */
577 volatile u_int32_t BB_bt_coex_1; /* 0x54 - 0x58 */
578 volatile u_int32_t BB_bt_coex_2; /* 0x58 - 0x5c */
579 volatile u_int32_t BB_bt_coex_3; /* 0x5c - 0x60 */
580 volatile u_int32_t BB_bt_coex_4; /* 0x60 - 0x64 */
581 volatile u_int32_t BB_bt_coex_5; /* 0x64 - 0x68 */
582 volatile u_int32_t BB_redpwr_ctrl_1; /* 0x68 - 0x6c */
583 volatile u_int32_t BB_redpwr_ctrl_2; /* 0x6c - 0x70 */
585 volatile u_int32_t BB_rssi_b0; /* 0x180 - 0x184 */
586 volatile u_int32_t BB_spur_est_cck_report_b0; /* 0x184 - 0x188 */
587 volatile u_int32_t BB_agc_dig_dc_status_i_b0; /* 0x188 - 0x18c */
588 volatile u_int32_t BB_agc_dig_dc_status_q_b0; /* 0x18c - 0x190 */
589 volatile u_int32_t BB_dc_cal_status_b0; /* 0x190 - 0x194 */
591 volatile u_int32_t BB_bbb_sig_detect; /* 0x1c0 - 0x1c4 */
592 volatile u_int32_t BB_bbb_dagc_ctrl; /* 0x1c4 - 0x1c8 */
593 volatile u_int32_t BB_iqcorr_ctrl_cck; /* 0x1c8 - 0x1cc */
594 volatile u_int32_t BB_cck_spur_mit; /* 0x1cc - 0x1d0 */
595 volatile u_int32_t BB_mrc_cck_ctrl; /* 0x1d0 - 0x1d4 */
596 volatile u_int32_t BB_cck_blocker_det; /* 0x1d4 - 0x1d8 */
598 volatile u_int32_t BB_rx_ocgain[128]; /* 0x200 - 0x400 */
602 volatile u_int32_t BB_D2_chip_id; /* 0x0 - 0x4 */
603 volatile u_int32_t BB_gen_controls; /* 0x4 - 0x8 */
604 volatile u_int32_t BB_modes_select; /* 0x8 - 0xc */
605 volatile u_int32_t BB_active; /* 0xc - 0x10 */
607 volatile u_int32_t BB_vit_spur_mask_A; /* 0x20 - 0x24 */
608 volatile u_int32_t BB_vit_spur_mask_B; /* 0x24 - 0x28 */
609 volatile u_int32_t BB_spectral_scan; /* 0x28 - 0x2c */
610 volatile u_int32_t BB_radar_bw_filter; /* 0x2c - 0x30 */
611 volatile u_int32_t BB_search_start_delay; /* 0x30 - 0x34 */
612 volatile u_int32_t BB_max_rx_length; /* 0x34 - 0x38 */
613 volatile u_int32_t BB_frame_control; /* 0x38 - 0x3c */
614 volatile u_int32_t BB_rfbus_request; /* 0x3c - 0x40 */
615 volatile u_int32_t BB_rfbus_grant; /* 0x40 - 0x44 */
616 volatile u_int32_t BB_rifs; /* 0x44 - 0x48 */
617 volatile u_int32_t BB_spectral_scan_2; /* 0x48 - 0x4c */
619 volatile u_int32_t BB_rx_clear_delay; /* 0x50 - 0x54 */
620 volatile u_int32_t BB_analog_power_on_time; /* 0x54 - 0x58 */
621 volatile u_int32_t BB_tx_timing_1; /* 0x58 - 0x5c */
622 volatile u_int32_t BB_tx_timing_2; /* 0x5c - 0x60 */
623 volatile u_int32_t BB_tx_timing_3; /* 0x60 - 0x64 */
624 volatile u_int32_t BB_xpa_timing_control; /* 0x64 - 0x68 */
626 volatile u_int32_t BB_misc_pa_control; /* 0x80 - 0x84 */
627 volatile u_int32_t BB_switch_table_chn_b0; /* 0x84 - 0x88 */
628 volatile u_int32_t BB_switch_table_com1; /* 0x88 - 0x8c */
629 volatile u_int32_t BB_switch_table_com2; /* 0x8c - 0x90 */
631 volatile u_int32_t BB_multichain_enable; /* 0xa0 - 0xa4 */
633 volatile u_int32_t BB_cal_chain_mask; /* 0xc0 - 0xc4 */
634 volatile u_int32_t BB_agc_control; /* 0xc4 - 0xc8 */
635 volatile u_int32_t BB_iq_adc_cal_mode; /* 0xc8 - 0xcc */
636 volatile u_int32_t BB_fcal_1; /* 0xcc - 0xd0 */
637 volatile u_int32_t BB_fcal_2_b0; /* 0xd0 - 0xd4 */
638 volatile u_int32_t BB_dft_tone_ctrl_b0; /* 0xd4 - 0xd8 */
639 volatile u_int32_t BB_cl_cal_ctrl; /* 0xd8 - 0xdc */
640 volatile u_int32_t BB_cl_map_0_b0; /* 0xdc - 0xe0 */
641 volatile u_int32_t BB_cl_map_1_b0; /* 0xe0 - 0xe4 */
642 volatile u_int32_t BB_cl_map_2_b0; /* 0xe4 - 0xe8 */
643 volatile u_int32_t BB_cl_map_3_b0; /* 0xe8 - 0xec */
644 volatile u_int32_t BB_cl_map_pal_0_b0; /* 0xec - 0xf0 */
645 volatile u_int32_t BB_cl_map_pal_1_b0; /* 0xf0 - 0xf4 */
646 volatile u_int32_t BB_cl_map_pal_2_b0; /* 0xf4 - 0xf8 */
647 volatile u_int32_t BB_cl_map_pal_3_b0; /* 0xf8 - 0xfc */
649 volatile u_int32_t BB_cl_tab_b0[16]; /* 0x100 - 0x140 */
650 volatile u_int32_t BB_synth_control; /* 0x140 - 0x144 */
651 volatile u_int32_t BB_addac_clk_select; /* 0x144 - 0x148 */
652 volatile u_int32_t BB_pll_cntl; /* 0x148 - 0x14c */
653 volatile u_int32_t BB_analog_swap; /* 0x14c - 0x150 */
654 volatile u_int32_t BB_addac_parallel_control; /* 0x150 - 0x154 */
656 volatile u_int32_t BB_force_analog; /* 0x158 - 0x15c */
658 volatile u_int32_t BB_test_controls; /* 0x160 - 0x164 */
659 volatile u_int32_t BB_test_controls_status; /* 0x164 - 0x168 */
660 volatile u_int32_t BB_tstdac; /* 0x168 - 0x16c */
661 volatile u_int32_t BB_channel_status; /* 0x16c - 0x170 */
662 volatile u_int32_t BB_chaninfo_ctrl; /* 0x170 - 0x174 */
663 volatile u_int32_t BB_chan_info_noise_pwr; /* 0x174 - 0x178 */
664 volatile u_int32_t BB_chan_info_gain_diff; /* 0x178 - 0x17c */
665 volatile u_int32_t BB_chan_info_fine_timing; /* 0x17c - 0x180 */
666 volatile u_int32_t BB_chan_info_gain_b0; /* 0x180 - 0x184 */
668 volatile u_int32_t BB_scrambler_seed; /* 0x190 - 0x194 */
669 volatile u_int32_t BB_bbb_tx_ctrl; /* 0x194 - 0x198 */
670 volatile u_int32_t BB_bbb_txfir_0; /* 0x198 - 0x19c */
671 volatile u_int32_t BB_bbb_txfir_1; /* 0x19c - 0x1a0 */
672 volatile u_int32_t BB_bbb_txfir_2; /* 0x1a0 - 0x1a4 */
673 volatile u_int32_t BB_heavy_clip_ctrl; /* 0x1a4 - 0x1a8 */
674 volatile u_int32_t BB_heavy_clip_20; /* 0x1a8 - 0x1ac */
675 volatile u_int32_t BB_heavy_clip_40; /* 0x1ac - 0x1b0 */
676 volatile u_int32_t BB_illegal_tx_rate; /* 0x1b0 - 0x1b4 */
678 volatile u_int32_t BB_powertx_rate1; /* 0x1c0 - 0x1c4 */
679 volatile u_int32_t BB_powertx_rate2; /* 0x1c4 - 0x1c8 */
680 volatile u_int32_t BB_powertx_rate3; /* 0x1c8 - 0x1cc */
681 volatile u_int32_t BB_powertx_rate4; /* 0x1cc - 0x1d0 */
682 volatile u_int32_t BB_powertx_rate5; /* 0x1d0 - 0x1d4 */
683 volatile u_int32_t BB_powertx_rate6; /* 0x1d4 - 0x1d8 */
684 volatile u_int32_t BB_powertx_rate7; /* 0x1d8 - 0x1dc */
685 volatile u_int32_t BB_powertx_rate8; /* 0x1dc - 0x1e0 */
686 volatile u_int32_t BB_powertx_rate9; /* 0x1e0 - 0x1e4 */
687 volatile u_int32_t BB_powertx_rate10; /* 0x1e4 - 0x1e8 */
688 volatile u_int32_t BB_powertx_rate11; /* 0x1e8 - 0x1ec */
689 volatile u_int32_t BB_powertx_rate12; /* 0x1ec - 0x1f0 */
690 volatile u_int32_t BB_powertx_max; /* 0x1f0 - 0x1f4 */
691 volatile u_int32_t BB_powertx_sub; /* 0x1f4 - 0x1f8 */
692 volatile u_int32_t BB_tpc_1; /* 0x1f8 - 0x1fc */
693 volatile u_int32_t BB_tpc_2; /* 0x1fc - 0x200 */
694 volatile u_int32_t BB_tpc_3; /* 0x200 - 0x204 */
695 volatile u_int32_t BB_tpc_4_b0; /* 0x204 - 0x208 */
696 volatile u_int32_t BB_tpc_5_b0; /* 0x208 - 0x20c */
697 volatile u_int32_t BB_tpc_6_b0; /* 0x20c - 0x210 */
698 volatile u_int32_t BB_tpc_7; /* 0x210 - 0x214 */
699 volatile u_int32_t BB_tpc_8; /* 0x214 - 0x218 */
700 volatile u_int32_t BB_tpc_9; /* 0x218 - 0x21c */
701 volatile u_int32_t BB_tpc_10; /* 0x21c - 0x220 */
702 volatile u_int32_t BB_tpc_11_b0; /* 0x220 - 0x224 */
703 volatile u_int32_t BB_tpc_12; /* 0x224 - 0x228 */
704 volatile u_int32_t BB_tpc_13; /* 0x228 - 0x22c */
705 volatile u_int32_t BB_tpc_14; /* 0x22c - 0x230 */
706 volatile u_int32_t BB_tpc_15; /* 0x230 - 0x234 */
707 volatile u_int32_t BB_tpc_16; /* 0x234 - 0x238 */
708 volatile u_int32_t BB_tpc_17; /* 0x238 - 0x23c */
709 volatile u_int32_t BB_tpc_18; /* 0x23c - 0x240 */
710 volatile u_int32_t BB_tpc_19_b0; /* 0x240 - 0x244 */
711 volatile u_int32_t BB_tpc_20; /* 0x244 - 0x248 */
712 volatile u_int32_t BB_therm_adc_1; /* 0x248 - 0x24c */
713 volatile u_int32_t BB_therm_adc_2; /* 0x24c - 0x250 */
714 volatile u_int32_t BB_therm_adc_3; /* 0x250 - 0x254 */
715 volatile u_int32_t BB_therm_adc_4; /* 0x254 - 0x258 */
716 volatile u_int32_t BB_tx_forced_gain; /* 0x258 - 0x25c */
718 volatile u_int32_t BB_pdadc_tab_b0[32]; /* 0x280 - 0x300 */
719 volatile u_int32_t BB_tx_gain_tab_1; /* 0x300 - 0x304 */
720 volatile u_int32_t BB_tx_gain_tab_2; /* 0x304 - 0x308 */
721 volatile u_int32_t BB_tx_gain_tab_3; /* 0x308 - 0x30c */
722 volatile u_int32_t BB_tx_gain_tab_4; /* 0x30c - 0x310 */
723 volatile u_int32_t BB_tx_gain_tab_5; /* 0x310 - 0x314 */
724 volatile u_int32_t BB_tx_gain_tab_6; /* 0x314 - 0x318 */
725 volatile u_int32_t BB_tx_gain_tab_7; /* 0x318 - 0x31c */
726 volatile u_int32_t BB_tx_gain_tab_8; /* 0x31c - 0x320 */
727 volatile u_int32_t BB_tx_gain_tab_9; /* 0x320 - 0x324 */
728 volatile u_int32_t BB_tx_gain_tab_10; /* 0x324 - 0x328 */
729 volatile u_int32_t BB_tx_gain_tab_11; /* 0x328 - 0x32c */
730 volatile u_int32_t BB_tx_gain_tab_12; /* 0x32c - 0x330 */
731 volatile u_int32_t BB_tx_gain_tab_13; /* 0x330 - 0x334 */
732 volatile u_int32_t BB_tx_gain_tab_14; /* 0x334 - 0x338 */
733 volatile u_int32_t BB_tx_gain_tab_15; /* 0x338 - 0x33c */
734 volatile u_int32_t BB_tx_gain_tab_16; /* 0x33c - 0x340 */
735 volatile u_int32_t BB_tx_gain_tab_17; /* 0x340 - 0x344 */
736 volatile u_int32_t BB_tx_gain_tab_18; /* 0x344 - 0x348 */
737 volatile u_int32_t BB_tx_gain_tab_19; /* 0x348 - 0x34c */
738 volatile u_int32_t BB_tx_gain_tab_20; /* 0x34c - 0x350 */
739 volatile u_int32_t BB_tx_gain_tab_21; /* 0x350 - 0x354 */
740 volatile u_int32_t BB_tx_gain_tab_22; /* 0x354 - 0x358 */
741 volatile u_int32_t BB_tx_gain_tab_23; /* 0x358 - 0x35c */
742 volatile u_int32_t BB_tx_gain_tab_24; /* 0x35c - 0x360 */
743 volatile u_int32_t BB_tx_gain_tab_25; /* 0x360 - 0x364 */
744 volatile u_int32_t BB_tx_gain_tab_26; /* 0x364 - 0x368 */
745 volatile u_int32_t BB_tx_gain_tab_27; /* 0x368 - 0x36c */
746 volatile u_int32_t BB_tx_gain_tab_28; /* 0x36c - 0x370 */
747 volatile u_int32_t BB_tx_gain_tab_29; /* 0x370 - 0x374 */
748 volatile u_int32_t BB_tx_gain_tab_30; /* 0x374 - 0x378 */
749 volatile u_int32_t BB_tx_gain_tab_31; /* 0x378 - 0x37c */
750 volatile u_int32_t BB_tx_gain_tab_32; /* 0x37c - 0x380 */
751 volatile u_int32_t BB_rtt_ctrl; /* 0x380 - 0x384 */
752 volatile u_int32_t BB_rtt_table_sw_intf_b0; /* 0x384 - 0x388 */
753 volatile u_int32_t BB_rtt_table_sw_intf_1_b0; /* 0x388 - 0x38c */
755 volatile u_int32_t BB_caltx_gain_set_0; /* 0x400 - 0x404 */
756 volatile u_int32_t BB_caltx_gain_set_2; /* 0x404 - 0x408 */
757 volatile u_int32_t BB_caltx_gain_set_4; /* 0x408 - 0x40c */
758 volatile u_int32_t BB_caltx_gain_set_6; /* 0x40c - 0x410 */
759 volatile u_int32_t BB_caltx_gain_set_8; /* 0x410 - 0x414 */
760 volatile u_int32_t BB_caltx_gain_set_10; /* 0x414 - 0x418 */
761 volatile u_int32_t BB_caltx_gain_set_12; /* 0x418 - 0x41c */
762 volatile u_int32_t BB_caltx_gain_set_14; /* 0x41c - 0x420 */
763 volatile u_int32_t BB_caltx_gain_set_16; /* 0x420 - 0x424 */
764 volatile u_int32_t BB_caltx_gain_set_18; /* 0x424 - 0x428 */
765 volatile u_int32_t BB_caltx_gain_set_20; /* 0x428 - 0x42c */
766 volatile u_int32_t BB_caltx_gain_set_22; /* 0x42c - 0x430 */
767 volatile u_int32_t BB_caltx_gain_set_24; /* 0x430 - 0x434 */
768 volatile u_int32_t BB_caltx_gain_set_26; /* 0x434 - 0x438 */
769 volatile u_int32_t BB_caltx_gain_set_28; /* 0x438 - 0x43c */
770 volatile u_int32_t BB_caltx_gain_set_30; /* 0x43c - 0x440 */
772 volatile u_int32_t BB_txiqcal_control_0; /* 0x444 - 0x448 */
773 volatile u_int32_t BB_txiqcal_control_1; /* 0x448 - 0x44c */
774 volatile u_int32_t BB_txiqcal_control_2; /* 0x44c - 0x450 */
775 volatile u_int32_t BB_txiq_corr_coeff_01_b0; /* 0x450 - 0x454 */
776 volatile u_int32_t BB_txiq_corr_coeff_23_b0; /* 0x454 - 0x458 */
777 volatile u_int32_t BB_txiq_corr_coeff_45_b0; /* 0x458 - 0x45c */
778 volatile u_int32_t BB_txiq_corr_coeff_67_b0; /* 0x45c - 0x460 */
779 volatile u_int32_t BB_txiq_corr_coeff_89_b0; /* 0x460 - 0x464 */
780 volatile u_int32_t BB_txiq_corr_coeff_ab_b0; /* 0x464 - 0x468 */
781 volatile u_int32_t BB_txiq_corr_coeff_cd_b0; /* 0x468 - 0x46c */
782 volatile u_int32_t BB_txiq_corr_coeff_ef_b0; /* 0x46c - 0x470 */
783 volatile u_int32_t BB_cal_rxbb_gain_tbl_0; /* 0x470 - 0x474 */
784 volatile u_int32_t BB_cal_rxbb_gain_tbl_4; /* 0x474 - 0x478 */
785 volatile u_int32_t BB_cal_rxbb_gain_tbl_8; /* 0x478 - 0x47c */
786 volatile u_int32_t BB_cal_rxbb_gain_tbl_12; /* 0x47c - 0x480 */
787 volatile u_int32_t BB_cal_rxbb_gain_tbl_16; /* 0x480 - 0x484 */
788 volatile u_int32_t BB_cal_rxbb_gain_tbl_20; /* 0x484 - 0x488 */
789 volatile u_int32_t BB_cal_rxbb_gain_tbl_24; /* 0x488 - 0x48c */
790 volatile u_int32_t BB_txiqcal_status_b0; /* 0x48c - 0x490 */
791 volatile u_int32_t BB_paprd_trainer_cntl1; /* 0x490 - 0x494 */
792 volatile u_int32_t BB_paprd_trainer_cntl2; /* 0x494 - 0x498 */
793 volatile u_int32_t BB_paprd_trainer_cntl3; /* 0x498 - 0x49c */
794 volatile u_int32_t BB_paprd_trainer_cntl4; /* 0x49c - 0x4a0 */
795 volatile u_int32_t BB_paprd_trainer_stat1; /* 0x4a0 - 0x4a4 */
796 volatile u_int32_t BB_paprd_trainer_stat2; /* 0x4a4 - 0x4a8 */
797 volatile u_int32_t BB_paprd_trainer_stat3; /* 0x4a8 - 0x4ac */
799 volatile u_int32_t BB_watchdog_status; /* 0x5c0 - 0x5c4 */
800 volatile u_int32_t BB_watchdog_ctrl_1; /* 0x5c4 - 0x5c8 */
801 volatile u_int32_t BB_watchdog_ctrl_2; /* 0x5c8 - 0x5cc */
802 volatile u_int32_t BB_bluetooth_cntl; /* 0x5cc - 0x5d0 */
803 volatile u_int32_t BB_phyonly_warm_reset; /* 0x5d0 - 0x5d4 */
804 volatile u_int32_t BB_phyonly_control; /* 0x5d4 - 0x5d8 */
806 volatile u_int32_t BB_eco_ctrl; /* 0x5dc - 0x5e0 */
808 volatile u_int32_t BB_tables_intf_addr_b0; /* 0x5f0 - 0x5f4 */
809 volatile u_int32_t BB_tables_intf_data_b0; /* 0x5f4 - 0x5f8 */
814 volatile u_int32_t BB_ext_chan_pwr_thr_2_b1; /* 0x30 - 0x34 */
816 volatile u_int32_t BB_spur_report_b1; /* 0xa8 - 0xac */
818 volatile u_int32_t BB_iq_adc_meas_0_b1; /* 0xc0 - 0xc4 */
819 volatile u_int32_t BB_iq_adc_meas_1_b1; /* 0xc4 - 0xc8 */
820 volatile u_int32_t BB_iq_adc_meas_2_b1; /* 0xc8 - 0xcc */
821 volatile u_int32_t BB_iq_adc_meas_3_b1; /* 0xcc - 0xd0 */
822 volatile u_int32_t BB_tx_phase_ramp_b1; /* 0xd0 - 0xd4 */
823 volatile u_int32_t BB_adc_gain_dc_corr_b1; /* 0xd4 - 0xd8 */
825 volatile u_int32_t BB_rx_iq_corr_b1; /* 0xdc - 0xe0 */
827 volatile u_int32_t BB_paprd_ctrl0_b1; /* 0xf0 - 0xf4 */
828 volatile u_int32_t BB_paprd_ctrl1_b1; /* 0xf4 - 0xf8 */
829 volatile u_int32_t BB_pa_gain123_b1; /* 0xf8 - 0xfc */
830 volatile u_int32_t BB_pa_gain45_b1; /* 0xfc - 0x100 */
831 volatile u_int32_t BB_paprd_pre_post_scale_0_b1;
833 volatile u_int32_t BB_paprd_pre_post_scale_1_b1;
835 volatile u_int32_t BB_paprd_pre_post_scale_2_b1;
837 volatile u_int32_t BB_paprd_pre_post_scale_3_b1;
839 volatile u_int32_t BB_paprd_pre_post_scale_4_b1;
841 volatile u_int32_t BB_paprd_pre_post_scale_5_b1;
843 volatile u_int32_t BB_paprd_pre_post_scale_6_b1;
845 volatile u_int32_t BB_paprd_pre_post_scale_7_b1;
847 volatile u_int32_t BB_paprd_mem_tab_b1[120]; /* 0x120 - 0x300 */
848 volatile u_int32_t BB_chan_info_chan_tab_b1[60];
850 volatile u_int32_t BB_chn1_tables_intf_addr; /* 0x3f0 - 0x3f4 */
851 volatile u_int32_t BB_chn1_tables_intf_data; /* 0x3f4 - 0x3f8 */
856 volatile u_int32_t BB_gain_force_max_gains_b1; /* 0x4 - 0x8 */
858 volatile u_int32_t BB_ext_atten_switch_ctl_b1; /* 0x18 - 0x1c */
859 volatile u_int32_t BB_cca_b1; /* 0x1c - 0x20 */
860 volatile u_int32_t BB_cca_ctrl_2_b1; /* 0x20 - 0x24 */
862 volatile u_int32_t BB_rssi_b1; /* 0x180 - 0x184 */
863 volatile u_int32_t BB_spur_est_cck_report_b1; /* 0x184 - 0x188 */
864 volatile u_int32_t BB_agc_dig_dc_status_i_b1; /* 0x188 - 0x18c */
865 volatile u_int32_t BB_agc_dig_dc_status_q_b1; /* 0x18c - 0x190 */
866 volatile u_int32_t BB_dc_cal_status_b1; /* 0x190 - 0x194 */
868 volatile u_int32_t BB_rx_ocgain2[128]; /* 0x200 - 0x400 */
873 volatile u_int32_t BB_switch_table_chn_b1; /* 0x84 - 0x88 */
875 volatile u_int32_t BB_fcal_2_b1; /* 0xd0 - 0xd4 */
876 volatile u_int32_t BB_dft_tone_ctrl_b1; /* 0xd4 - 0xd8 */
878 volatile u_int32_t BB_cl_map_0_b1; /* 0xdc - 0xe0 */
879 volatile u_int32_t BB_cl_map_1_b1; /* 0xe0 - 0xe4 */
880 volatile u_int32_t BB_cl_map_2_b1; /* 0xe4 - 0xe8 */
881 volatile u_int32_t BB_cl_map_3_b1; /* 0xe8 - 0xec */
882 volatile u_int32_t BB_cl_map_pal_0_b1; /* 0xec - 0xf0 */
883 volatile u_int32_t BB_cl_map_pal_1_b1; /* 0xf0 - 0xf4 */
884 volatile u_int32_t BB_cl_map_pal_2_b1; /* 0xf4 - 0xf8 */
885 volatile u_int32_t BB_cl_map_pal_3_b1; /* 0xf8 - 0xfc */
887 volatile u_int32_t BB_cl_tab_b1[16]; /* 0x100 - 0x140 */
889 volatile u_int32_t BB_chan_info_gain_b1; /* 0x180 - 0x184 */
891 volatile u_int32_t BB_tpc_4_b1; /* 0x204 - 0x208 */
892 volatile u_int32_t BB_tpc_5_b1; /* 0x208 - 0x20c */
893 volatile u_int32_t BB_tpc_6_b1; /* 0x20c - 0x210 */
895 volatile u_int32_t BB_tpc_11_b1; /* 0x220 - 0x224 */
897 volatile u_int32_t BB_tpc_19_b1; /* 0x240 - 0x244 */
899 volatile u_int32_t BB_pdadc_tab_b1[32]; /* 0x280 - 0x300 */
901 volatile u_int32_t BB_rtt_table_sw_intf_b1; /* 0x384 - 0x388 */
902 volatile u_int32_t BB_rtt_table_sw_intf_1_b1; /* 0x388 - 0x38c */
904 volatile u_int32_t BB_txiq_corr_coeff_01_b1; /* 0x450 - 0x454 */
905 volatile u_int32_t BB_txiq_corr_coeff_23_b1; /* 0x454 - 0x458 */
906 volatile u_int32_t BB_txiq_corr_coeff_45_b1; /* 0x458 - 0x45c */
907 volatile u_int32_t BB_txiq_corr_coeff_67_b1; /* 0x45c - 0x460 */
908 volatile u_int32_t BB_txiq_corr_coeff_89_b1; /* 0x460 - 0x464 */
909 volatile u_int32_t BB_txiq_corr_coeff_ab_b1; /* 0x464 - 0x468 */
910 volatile u_int32_t BB_txiq_corr_coeff_cd_b1; /* 0x468 - 0x46c */
911 volatile u_int32_t BB_txiq_corr_coeff_ef_b1; /* 0x46c - 0x470 */
913 volatile u_int32_t BB_txiqcal_status_b1; /* 0x48c - 0x490 */
915 volatile u_int32_t BB_tables_intf_addr_b1; /* 0x5f0 - 0x5f4 */
916 volatile u_int32_t BB_tables_intf_data_b1; /* 0x5f4 - 0x5f8 */
921 volatile u_int32_t BB_ext_chan_pwr_thr_2_b2; /* 0x30 - 0x34 */
923 volatile u_int32_t BB_spur_report_b2; /* 0xa8 - 0xac */
925 volatile u_int32_t BB_iq_adc_meas_0_b2; /* 0xc0 - 0xc4 */
926 volatile u_int32_t BB_iq_adc_meas_1_b2; /* 0xc4 - 0xc8 */
927 volatile u_int32_t BB_iq_adc_meas_2_b2; /* 0xc8 - 0xcc */
928 volatile u_int32_t BB_iq_adc_meas_3_b2; /* 0xcc - 0xd0 */
929 volatile u_int32_t BB_tx_phase_ramp_b2; /* 0xd0 - 0xd4 */
930 volatile u_int32_t BB_adc_gain_dc_corr_b2; /* 0xd4 - 0xd8 */
932 volatile u_int32_t BB_rx_iq_corr_b2; /* 0xdc - 0xe0 */
934 volatile u_int32_t BB_paprd_ctrl0_b2; /* 0xf0 - 0xf4 */
935 volatile u_int32_t BB_paprd_ctrl1_b2; /* 0xf4 - 0xf8 */
936 volatile u_int32_t BB_pa_gain123_b2; /* 0xf8 - 0xfc */
937 volatile u_int32_t BB_pa_gain45_b2; /* 0xfc - 0x100 */
938 volatile u_int32_t BB_paprd_pre_post_scale_0_b2;
940 volatile u_int32_t BB_paprd_pre_post_scale_1_b2;
942 volatile u_int32_t BB_paprd_pre_post_scale_2_b2;
944 volatile u_int32_t BB_paprd_pre_post_scale_3_b2;
946 volatile u_int32_t BB_paprd_pre_post_scale_4_b2;
948 volatile u_int32_t BB_paprd_pre_post_scale_5_b2;
950 volatile u_int32_t BB_paprd_pre_post_scale_6_b2;
952 volatile u_int32_t BB_paprd_pre_post_scale_7_b2;
954 volatile u_int32_t BB_paprd_mem_tab_b2[120]; /* 0x120 - 0x300 */
955 volatile u_int32_t BB_chan_info_chan_tab_b2[60];
957 volatile u_int32_t BB_chn2_tables_intf_addr; /* 0x3f0 - 0x3f4 */
958 volatile u_int32_t BB_chn2_tables_intf_data; /* 0x3f4 - 0x3f8 */
963 volatile u_int32_t BB_gain_force_max_gains_b2; /* 0x4 - 0x8 */
965 volatile u_int32_t BB_ext_atten_switch_ctl_b2; /* 0x18 - 0x1c */
966 volatile u_int32_t BB_cca_b2; /* 0x1c - 0x20 */
967 volatile u_int32_t BB_cca_ctrl_2_b2; /* 0x20 - 0x24 */
969 volatile u_int32_t BB_rssi_b2; /* 0x180 - 0x184 */
971 volatile u_int32_t BB_agc_dig_dc_status_i_b2; /* 0x188 - 0x18c */
972 volatile u_int32_t BB_agc_dig_dc_status_q_b2; /* 0x18c - 0x190 */
973 volatile u_int32_t BB_dc_cal_status_b2; /* 0x190 - 0x194 */
978 volatile u_int32_t BB_switch_table_chn_b2; /* 0x84 - 0x88 */
980 volatile u_int32_t BB_fcal_2_b2; /* 0xd0 - 0xd4 */
981 volatile u_int32_t BB_dft_tone_ctrl_b2; /* 0xd4 - 0xd8 */
983 volatile u_int32_t BB_cl_map_0_b2; /* 0xdc - 0xe0 */
984 volatile u_int32_t BB_cl_map_1_b2; /* 0xe0 - 0xe4 */
985 volatile u_int32_t BB_cl_map_2_b2; /* 0xe4 - 0xe8 */
986 volatile u_int32_t BB_cl_map_3_b2; /* 0xe8 - 0xec */
987 volatile u_int32_t BB_cl_map_pal_0_b2; /* 0xec - 0xf0 */
988 volatile u_int32_t BB_cl_map_pal_1_b2; /* 0xf0 - 0xf4 */
989 volatile u_int32_t BB_cl_map_pal_2_b2; /* 0xf4 - 0xf8 */
990 volatile u_int32_t BB_cl_map_pal_3_b2; /* 0xf8 - 0xfc */
992 volatile u_int32_t BB_cl_tab_b2[16]; /* 0x100 - 0x140 */
994 volatile u_int32_t BB_chan_info_gain_b2; /* 0x180 - 0x184 */
996 volatile u_int32_t BB_tpc_4_b2; /* 0x204 - 0x208 */
997 volatile u_int32_t BB_tpc_5_b2; /* 0x208 - 0x20c */
998 volatile u_int32_t BB_tpc_6_b2; /* 0x20c - 0x210 */
1000 volatile u_int32_t BB_tpc_11_b2; /* 0x220 - 0x224 */
1002 volatile u_int32_t BB_tpc_19_b2; /* 0x240 - 0x244 */
1004 volatile u_int32_t BB_pdadc_tab_b2[32]; /* 0x280 - 0x300 */
1006 volatile u_int32_t BB_rtt_table_sw_intf_b2; /* 0x384 - 0x388 */
1007 volatile u_int32_t BB_rtt_table_sw_intf_1_b2; /* 0x388 - 0x38c */
1009 volatile u_int32_t BB_txiq_corr_coeff_01_b2; /* 0x450 - 0x454 */
1010 volatile u_int32_t BB_txiq_corr_coeff_23_b2; /* 0x454 - 0x458 */
1011 volatile u_int32_t BB_txiq_corr_coeff_45_b2; /* 0x458 - 0x45c */
1012 volatile u_int32_t BB_txiq_corr_coeff_67_b2; /* 0x45c - 0x460 */
1013 volatile u_int32_t BB_txiq_corr_coeff_89_b2; /* 0x460 - 0x464 */
1014 volatile u_int32_t BB_txiq_corr_coeff_ab_b2; /* 0x464 - 0x468 */
1015 volatile u_int32_t BB_txiq_corr_coeff_cd_b2; /* 0x468 - 0x46c */
1016 volatile u_int32_t BB_txiq_corr_coeff_ef_b2; /* 0x46c - 0x470 */
1018 volatile u_int32_t BB_txiqcal_status_b2; /* 0x48c - 0x490 */
1020 volatile u_int32_t BB_tables_intf_addr_b2; /* 0x5f0 - 0x5f4 */
1021 volatile u_int32_t BB_tables_intf_data_b2; /* 0x5f4 - 0x5f8 */
1025 volatile u_int32_t BB_dummy1[256]; /* 0x0 - 0x400 */
1029 volatile u_int32_t BB_dummy; /* 0x0 - 0x4 */
1031 volatile u_int32_t BB_rssi_b3; /* 0x180 - 0x184 */
1035 volatile u_int32_t BB_dummy2[384]; /* 0x0 - 0x600 */
1068 volatile u_int32_t MAC_PCU_BUF[2048]; /* 0x0 - 0x2000 */
1072 volatile u_int32_t TXBF_DBG; /* 0x0 - 0x4 */
1073 volatile u_int32_t TXBF; /* 0x4 - 0x8 */
1074 volatile u_int32_t TXBF_TIMER; /* 0x8 - 0xc */
1075 volatile u_int32_t TXBF_SW; /* 0xc - 0x10 */
1076 volatile u_int32_t TXBF_SM; /* 0x10 - 0x14 */
1077 volatile u_int32_t TXBF1_CNTL; /* 0x14 - 0x18 */
1078 volatile u_int32_t TXBF2_CNTL; /* 0x18 - 0x1c */
1079 volatile u_int32_t TXBF3_CNTL; /* 0x1c - 0x20 */
1080 volatile u_int32_t TXBF4_CNTL; /* 0x20 - 0x24 */
1081 volatile u_int32_t TXBF5_CNTL; /* 0x24 - 0x28 */
1082 volatile u_int32_t TXBF6_CNTL; /* 0x28 - 0x2c */
1083 volatile u_int32_t TXBF7_CNTL; /* 0x2c - 0x30 */
1084 volatile u_int32_t TXBF8_CNTL; /* 0x30 - 0x34 */
1086 volatile u_int32_t RC0[118]; /* 0x1000 - 0x11d8 */
1088 volatile u_int32_t RC1[118]; /* 0x1200 - 0x13d8 */
1090 volatile u_int32_t SVD_MEM0[114]; /* 0x1400 - 0x15c8 */
1092 volatile u_int32_t SVD_MEM1[114]; /* 0x1600 - 0x17c8 */
1094 volatile u_int32_t SVD_MEM2[114]; /* 0x1800 - 0x19c8 */
1096 volatile u_int32_t SVD_MEM3[114]; /* 0x1a00 - 0x1bc8 */
1098 volatile u_int32_t SVD_MEM4[114]; /* 0x1c00 - 0x1dc8 */
1100 volatile u_int32_t CVCACHE[512]; /* 0x2400 - 0x2c00 */
1104 volatile u_int32_t ch0_RXRF_BIAS1; /* 0x0 - 0x4 */
1105 volatile u_int32_t ch0_RXRF_BIAS2; /* 0x4 - 0x8 */
1106 volatile u_int32_t ch0_RXRF_GAINSTAGES; /* 0x8 - 0xc */
1107 volatile u_int32_t ch0_RXRF_AGC; /* 0xc - 0x10 */
1109 volatile u_int32_t ch0_TXRF1; /* 0x40 - 0x44 */
1110 volatile u_int32_t ch0_TXRF2; /* 0x44 - 0x48 */
1111 volatile u_int32_t ch0_TXRF3; /* 0x48 - 0x4c */
1112 volatile u_int32_t ch0_TXRF4; /* 0x4c - 0x50 */
1113 volatile u_int32_t ch0_TXRF5; /* 0x50 - 0x54 */
1114 volatile u_int32_t ch0_TXRF6; /* 0x54 - 0x58 */
1116 volatile u_int32_t ch0_SYNTH1; /* 0x80 - 0x84 */
1117 volatile u_int32_t ch0_SYNTH2; /* 0x84 - 0x88 */
1118 volatile u_int32_t ch0_SYNTH3; /* 0x88 - 0x8c */
1119 volatile u_int32_t ch0_SYNTH4; /* 0x8c - 0x90 */
1120 volatile u_int32_t ch0_SYNTH5; /* 0x90 - 0x94 */
1121 volatile u_int32_t ch0_SYNTH6; /* 0x94 - 0x98 */
1122 volatile u_int32_t ch0_SYNTH7; /* 0x98 - 0x9c */
1123 volatile u_int32_t ch0_SYNTH8; /* 0x9c - 0xa0 */
1124 volatile u_int32_t ch0_SYNTH9; /* 0xa0 - 0xa4 */
1125 volatile u_int32_t ch0_SYNTH10; /* 0xa4 - 0xa8 */
1126 volatile u_int32_t ch0_SYNTH11; /* 0xa8 - 0xac */
1127 volatile u_int32_t ch0_SYNTH12; /* 0xac - 0xb0 */
1128 volatile u_int32_t ch0_SYNTH13; /* 0xb0 - 0xb4 */
1129 volatile u_int32_t ch0_SYNTH14; /* 0xb4 - 0xb8 */
1131 volatile u_int32_t ch0_BIAS1; /* 0xc0 - 0xc4 */
1132 volatile u_int32_t ch0_BIAS2; /* 0xc4 - 0xc8 */
1133 volatile u_int32_t ch0_BIAS3; /* 0xc8 - 0xcc */
1134 volatile u_int32_t ch0_BIAS4; /* 0xcc - 0xd0 */
1136 volatile u_int32_t ch0_RXTX1; /* 0x100 - 0x104 */
1137 volatile u_int32_t ch0_RXTX2; /* 0x104 - 0x108 */
1138 volatile u_int32_t ch0_RXTX3; /* 0x108 - 0x10c */
1139 volatile u_int32_t ch0_RXTX4; /* 0x10c - 0x110 */
1141 volatile u_int32_t ch0_BB1; /* 0x140 - 0x144 */
1142 volatile u_int32_t ch0_BB2; /* 0x144 - 0x148 */
1143 volatile u_int32_t ch0_BB3; /* 0x148 - 0x14c */
1145 volatile u_int32_t ch0_BB_PLL; /* 0x180 - 0x184 */
1146 volatile u_int32_t ch0_BB_PLL2; /* 0x184 - 0x188 */
1147 volatile u_int32_t ch0_BB_PLL3; /* 0x188 - 0x18c */
1148 volatile u_int32_t ch0_BB_PLL4; /* 0x18c - 0x190 */
1150 volatile u_int32_t ch0_CPU_PLL; /* 0x1c0 - 0x1c4 */
1151 volatile u_int32_t ch0_CPU_PLL2; /* 0x1c4 - 0x1c8 */
1152 volatile u_int32_t ch0_CPU_PLL3; /* 0x1c8 - 0x1cc */
1153 volatile u_int32_t ch0_CPU_PLL4; /* 0x1cc - 0x1d0 */
1155 volatile u_int32_t ch0_AUDIO_PLL; /* 0x200 - 0x204 */
1156 volatile u_int32_t ch0_AUDIO_PLL2; /* 0x204 - 0x208 */
1157 volatile u_int32_t ch0_AUDIO_PLL3; /* 0x208 - 0x20c */
1158 volatile u_int32_t ch0_AUDIO_PLL4; /* 0x20c - 0x210 */
1160 volatile u_int32_t ch0_DDR_PLL; /* 0x240 - 0x244 */
1161 volatile u_int32_t ch0_DDR_PLL2; /* 0x244 - 0x248 */
1162 volatile u_int32_t ch0_DDR_PLL3; /* 0x248 - 0x24c */
1163 volatile u_int32_t ch0_DDR_PLL4; /* 0x24c - 0x250 */
1165 volatile u_int32_t ch0_TOP; /* 0x280 - 0x284 */
1166 volatile u_int32_t ch0_TOP2; /* 0x284 - 0x288 */
1167 volatile u_int32_t ch0_TOP3; /* 0x288 - 0x28c */
1168 volatile u_int32_t ch0_THERM; /* 0x28c - 0x290 */
1169 volatile u_int32_t ch0_XTAL; /* 0x290 - 0x294 */
1171 volatile u_int32_t ch0_rbist_cntrl; /* 0x380 - 0x384 */
1172 volatile u_int32_t ch0_tx_dc_offset; /* 0x384 - 0x388 */
1173 volatile u_int32_t ch0_tx_tonegen0; /* 0x388 - 0x38c */
1174 volatile u_int32_t ch0_tx_tonegen1; /* 0x38c - 0x390 */
1175 volatile u_int32_t ch0_tx_lftonegen0; /* 0x390 - 0x394 */
1176 volatile u_int32_t ch0_tx_linear_ramp_i; /* 0x394 - 0x398 */
1177 volatile u_int32_t ch0_tx_linear_ramp_q; /* 0x398 - 0x39c */
1178 volatile u_int32_t ch0_tx_prbs_mag; /* 0x39c - 0x3a0 */
1179 volatile u_int32_t ch0_tx_prbs_seed_i; /* 0x3a0 - 0x3a4 */
1180 volatile u_int32_t ch0_tx_prbs_seed_q; /* 0x3a4 - 0x3a8 */
1181 volatile u_int32_t ch0_cmac_dc_cancel; /* 0x3a8 - 0x3ac */
1182 volatile u_int32_t ch0_cmac_dc_offset; /* 0x3ac - 0x3b0 */
1183 volatile u_int32_t ch0_cmac_corr; /* 0x3b0 - 0x3b4 */
1184 volatile u_int32_t ch0_cmac_power; /* 0x3b4 - 0x3b8 */
1185 volatile u_int32_t ch0_cmac_cross_corr; /* 0x3b8 - 0x3bc */
1186 volatile u_int32_t ch0_cmac_i2q2; /* 0x3bc - 0x3c0 */
1187 volatile u_int32_t ch0_cmac_power_hpf; /* 0x3c0 - 0x3c4 */
1188 volatile u_int32_t ch0_rxdac_set1; /* 0x3c4 - 0x3c8 */
1189 volatile u_int32_t ch0_rxdac_set2; /* 0x3c8 - 0x3cc */
1190 volatile u_int32_t ch0_rxdac_long_shift; /* 0x3cc - 0x3d0 */
1191 volatile u_int32_t ch0_cmac_results_i; /* 0x3d0 - 0x3d4 */
1192 volatile u_int32_t ch0_cmac_results_q; /* 0x3d4 - 0x3d8 */
1194 volatile u_int32_t ch1_RXRF_BIAS1; /* 0x400 - 0x404 */
1195 volatile u_int32_t ch1_RXRF_BIAS2; /* 0x404 - 0x408 */
1196 volatile u_int32_t ch1_RXRF_GAINSTAGES; /* 0x408 - 0x40c */
1197 volatile u_int32_t ch1_RXRF_AGC; /* 0x40c - 0x410 */
1199 volatile u_int32_t ch1_TXRF1; /* 0x440 - 0x444 */
1200 volatile u_int32_t ch1_TXRF2; /* 0x444 - 0x448 */
1201 volatile u_int32_t ch1_TXRF3; /* 0x448 - 0x44c */
1202 volatile u_int32_t ch1_TXRF4; /* 0x44c - 0x450 */
1203 volatile u_int32_t ch1_TXRF5; /* 0x450 - 0x454 */
1204 volatile u_int32_t ch1_TXRF6; /* 0x454 - 0x458 */
1206 volatile u_int32_t ch1_RXTX1; /* 0x500 - 0x504 */
1207 volatile u_int32_t ch1_RXTX2; /* 0x504 - 0x508 */
1208 volatile u_int32_t ch1_RXTX3; /* 0x508 - 0x50c */
1209 volatile u_int32_t ch1_RXTX4; /* 0x50c - 0x510 */
1211 volatile u_int32_t ch1_BB1; /* 0x540 - 0x544 */
1212 volatile u_int32_t ch1_BB2; /* 0x544 - 0x548 */
1213 volatile u_int32_t ch1_BB3; /* 0x548 - 0x54c */
1215 volatile u_int32_t ch1_rbist_cntrl; /* 0x780 - 0x784 */
1216 volatile u_int32_t ch1_tx_dc_offset; /* 0x784 - 0x788 */
1217 volatile u_int32_t ch1_tx_tonegen0; /* 0x788 - 0x78c */
1218 volatile u_int32_t ch1_tx_tonegen1; /* 0x78c - 0x790 */
1219 volatile u_int32_t ch1_tx_lftonegen0; /* 0x790 - 0x794 */
1220 volatile u_int32_t ch1_tx_linear_ramp_i; /* 0x794 - 0x798 */
1221 volatile u_int32_t ch1_tx_linear_ramp_q; /* 0x798 - 0x79c */
1222 volatile u_int32_t ch1_tx_prbs_mag; /* 0x79c - 0x7a0 */
1223 volatile u_int32_t ch1_tx_prbs_seed_i; /* 0x7a0 - 0x7a4 */
1224 volatile u_int32_t ch1_tx_prbs_seed_q; /* 0x7a4 - 0x7a8 */
1225 volatile u_int32_t ch1_cmac_dc_cancel; /* 0x7a8 - 0x7ac */
1226 volatile u_int32_t ch1_cmac_dc_offset; /* 0x7ac - 0x7b0 */
1227 volatile u_int32_t ch1_cmac_corr; /* 0x7b0 - 0x7b4 */
1228 volatile u_int32_t ch1_cmac_power; /* 0x7b4 - 0x7b8 */
1229 volatile u_int32_t ch1_cmac_cross_corr; /* 0x7b8 - 0x7bc */
1230 volatile u_int32_t ch1_cmac_i2q2; /* 0x7bc - 0x7c0 */
1231 volatile u_int32_t ch1_cmac_power_hpf; /* 0x7c0 - 0x7c4 */
1232 volatile u_int32_t ch1_rxdac_set1; /* 0x7c4 - 0x7c8 */
1233 volatile u_int32_t ch1_rxdac_set2; /* 0x7c8 - 0x7cc */
1234 volatile u_int32_t ch1_rxdac_long_shift; /* 0x7cc - 0x7d0 */
1235 volatile u_int32_t ch1_cmac_results_i; /* 0x7d0 - 0x7d4 */
1236 volatile u_int32_t ch1_cmac_results_q; /* 0x7d4 - 0x7d8 */
1238 volatile u_int32_t ch2_RXRF_BIAS1; /* 0x800 - 0x804 */
1239 volatile u_int32_t ch2_RXRF_BIAS2; /* 0x804 - 0x808 */
1240 volatile u_int32_t ch2_RXRF_GAINSTAGES; /* 0x808 - 0x80c */
1241 volatile u_int32_t ch2_RXRF_AGC; /* 0x80c - 0x810 */
1243 volatile u_int32_t ch2_TXRF1; /* 0x840 - 0x844 */
1244 volatile u_int32_t ch2_TXRF2; /* 0x844 - 0x848 */
1245 volatile u_int32_t ch2_TXRF3; /* 0x848 - 0x84c */
1246 volatile u_int32_t ch2_TXRF4; /* 0x84c - 0x850 */
1247 volatile u_int32_t ch2_TXRF5; /* 0x850 - 0x854 */
1248 volatile u_int32_t ch2_TXRF6; /* 0x854 - 0x858 */
1250 volatile u_int32_t ch2_RXTX1; /* 0x900 - 0x904 */
1251 volatile u_int32_t ch2_RXTX2; /* 0x904 - 0x908 */
1252 volatile u_int32_t ch2_RXTX3; /* 0x908 - 0x90c */
1253 volatile u_int32_t ch2_RXTX4; /* 0x90c - 0x910 */
1255 volatile u_int32_t ch2_BB1; /* 0x940 - 0x944 */
1256 volatile u_int32_t ch2_BB2; /* 0x944 - 0x948 */
1257 volatile u_int32_t ch2_BB3; /* 0x948 - 0x94c */
1259 volatile u_int32_t ch2_rbist_cntrl; /* 0xb80 - 0xb84 */
1260 volatile u_int32_t ch2_tx_dc_offset; /* 0xb84 - 0xb88 */
1261 volatile u_int32_t ch2_tx_tonegen0; /* 0xb88 - 0xb8c */
1262 volatile u_int32_t ch2_tx_tonegen1; /* 0xb8c - 0xb90 */
1263 volatile u_int32_t ch2_tx_lftonegen0; /* 0xb90 - 0xb94 */
1264 volatile u_int32_t ch2_tx_linear_ramp_i; /* 0xb94 - 0xb98 */
1265 volatile u_int32_t ch2_tx_linear_ramp_q; /* 0xb98 - 0xb9c */
1266 volatile u_int32_t ch2_tx_prbs_mag; /* 0xb9c - 0xba0 */
1267 volatile u_int32_t ch2_tx_prbs_seed_i; /* 0xba0 - 0xba4 */
1268 volatile u_int32_t ch2_tx_prbs_seed_q; /* 0xba4 - 0xba8 */
1269 volatile u_int32_t ch2_cmac_dc_cancel; /* 0xba8 - 0xbac */
1270 volatile u_int32_t ch2_cmac_dc_offset; /* 0xbac - 0xbb0 */
1271 volatile u_int32_t ch2_cmac_corr; /* 0xbb0 - 0xbb4 */
1272 volatile u_int32_t ch2_cmac_power; /* 0xbb4 - 0xbb8 */
1273 volatile u_int32_t ch2_cmac_cross_corr; /* 0xbb8 - 0xbbc */
1274 volatile u_int32_t ch2_cmac_i2q2; /* 0xbbc - 0xbc0 */
1275 volatile u_int32_t ch2_cmac_power_hpf; /* 0xbc0 - 0xbc4 */
1276 volatile u_int32_t ch2_rxdac_set1; /* 0xbc4 - 0xbc8 */
1277 volatile u_int32_t ch2_rxdac_set2; /* 0xbc8 - 0xbcc */
1278 volatile u_int32_t ch2_rxdac_long_shift; /* 0xbcc - 0xbd0 */
1279 volatile u_int32_t ch2_cmac_results_i; /* 0xbd0 - 0xbd4 */
1280 volatile u_int32_t ch2_cmac_results_q; /* 0xbd4 - 0xbd8 */