ath_hal/ar9300/ar9300desc.h

30     u_int32_t   ds_info;
31     u_int32_t   status1;
32     u_int32_t   status2;
33     u_int32_t   status3;
34     u_int32_t   status4;
35     u_int32_t   status5;
36     u_int32_t   status6;
37     u_int32_t   status7;
38     u_int32_t   status8;
42     u_int32_t   ds_info;
43     u_int32_t   status1;
44     u_int32_t   status2;
45     u_int32_t   status3;
46     u_int32_t   status4;
47     u_int32_t   status5;
48     u_int32_t   status6;
49     u_int32_t   status7;
50     u_int32_t   status8;
51     u_int32_t   status9;
52     u_int32_t   status10;
53     u_int32_t   status11;
58     u_int32_t   ds_info;   /* descriptor information */
59     u_int32_t   ds_link;   /* link pointer */
60     u_int32_t   ds_data0;  /* data pointer to 1st buffer */
61     u_int32_t   ds_ctl3;   /* DMA control 3  */
62     u_int32_t   ds_data1;  /* data pointer to 2nd buffer */
63     u_int32_t   ds_ctl5;   /* DMA control 5  */
64     u_int32_t   ds_data2;  /* data pointer to 3rd buffer */
65     u_int32_t   ds_ctl7;   /* DMA control 7  */
66     u_int32_t   ds_data3;  /* data pointer to 4th buffer */
67     u_int32_t   ds_ctl9;   /* DMA control 9  */
68     u_int32_t   ds_ctl10;  /* DMA control 10 */
69     u_int32_t   ds_ctl11;  /* DMA control 11 */
70     u_int32_t   ds_ctl12;  /* DMA control 12 */
71     u_int32_t   ds_ctl13;  /* DMA control 13 */
72     u_int32_t   ds_ctl14;  /* DMA control 14 */
73     u_int32_t   ds_ctl15;  /* DMA control 15 */
74     u_int32_t   ds_ctl16;  /* DMA control 16 */
75     u_int32_t   ds_ctl17;  /* DMA control 17 */
76     u_int32_t   ds_ctl18;  /* DMA control 18 */
77     u_int32_t   ds_ctl19;  /* DMA control 19 */
78     u_int32_t   ds_ctl20;  /* DMA control 20 */
79     u_int32_t   ds_ctl21;  /* DMA control 21 */
80     u_int32_t   ds_ctl22;  /* DMA control 22 */
81     u_int32_t   ds_ctl23;  /* DMA control 23 */
82     u_int32_t   ds_pad[8]; /* pad to cache line (128 bytes/32 dwords) */
503 extern  u_int32_t ar9300_get_tx_dp(struct ath_hal *ah, u_int q);
504 extern  HAL_BOOL ar9300_set_tx_dp(struct ath_hal *ah, u_int q, u_int32_t txdp);
506 extern  u_int32_t ar9300_num_tx_pending(struct ath_hal *ah, u_int q);
510 extern  void ar9300_get_tx_intr_queue(struct ath_hal *ah, u_int32_t *);
514         u_int32_t *seg_len, u_int desc_id, u_int qcu, HAL_KEY_TYPE key_type, HAL_BOOL first_seg,
516 extern  void ar9300_set_desc_link(struct ath_hal *, void *ds, u_int32_t link);
517 extern  void ar9300_get_desc_link_ptr(struct ath_hal *, void *ds, u_int32_t **link);
523 extern  void ar9300_get_raw_tx_desc(struct ath_hal *ah, u_int32_t *);
525 extern  u_int32_t ar9300_calc_tx_airtime(struct ath_hal *ah, void *, struct ath_tx_status *,
527 extern  void ar9300_setup_tx_status_ring(struct ath_hal *ah, void *, u_int32_t , u_int16_t);
542        u_int nseries, u_int flags, u_int32_t smartAntenna);
563 extern  u_int32_t ar9300_get_rx_dp(struct ath_hal *ath, HAL_RX_QUEUE qtype);
564 extern  void ar9300_set_rx_dp(struct ath_hal *ah, u_int32_t rxdp, HAL_RX_QUEUE qtype);
570         u_int32_t filter0, u_int32_t filter1);
571 extern  u_int32_t ar9300_get_rx_filter(struct ath_hal *ah);
572 extern  void ar9300_set_rx_filter(struct ath_hal *ah, u_int32_t bits);
577         struct ath_desc *, u_int32_t, struct ath_desc *, u_int64_t, struct ath_rx_status *);
581         u_int32_t, struct ath_desc *, struct ath_rx_status *, void *);
584 extern  void ar9300_read_pktlog_reg(struct ath_hal *ah, u_int32_t *, u_int32_t *, u_int32_t *, u_int32_t *);
585 extern  void ar9300_write_pktlog_reg(struct ath_hal *ah, HAL_BOOL , u_int32_t , u_int32_t , u_int32_t , u_int32_t );