ath_hal/ar9300/ar9300_xmit.c

141     HAL_TX_QUEUE_INFO *qi;
188     qi = &ahp->ah_txq[q];
189     if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) {
195     OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO));
196     qi->tqi_type = type;
200         qi->tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
204         qi->tqi_aifs = INIT_AIFS;
205         qi->tqi_cwmin = HAL_TXQ_USEDEFAULT;     /* NB: do at reset */
206         qi->tqi_cwmax = INIT_CWMAX;
207         qi->tqi_shretry = INIT_SH_RETRY;
208         qi->tqi_lgretry = INIT_LG_RETRY;
209         qi->tqi_physCompBuf = 0;
211         qi->tqi_physCompBuf = q_info->tqi_compBuf;
222 set_tx_q_interrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)
252     HAL_TX_QUEUE_INFO *qi;
259     qi = &ahp->ah_txq[q];
260     if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
267     qi->tqi_type = HAL_TX_QUEUE_INACTIVE;
272     set_tx_q_interrupts(ah, qi);
289     HAL_TX_QUEUE_INFO       *qi;
298     qi = &ahp->ah_txq[q];
299     if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
306     if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) {
319         cw_min = qi->tqi_cwmin;
328                 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
329                 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
336         SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
351     if (qi->tqi_cbrPeriod) {
354             SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
355                 SM(qi->tqi_cbrOverflowLimit,
358             (qi->tqi_cbrOverflowLimit ?
362     if (qi->tqi_readyTime && (qi->tqi_type != HAL_TX_QUEUE_CAB)) {
364             SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
368     OS_REG_WRITE(ah, AR_DCHNTIME(q), SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
369                 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
371     if (qi->tqi_readyTime &&
372       (qi->tqi_qflags & HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE))
374     if (qi->tqi_qflags & HAL_TXQ_DBA_GATED)
380         if (qi->tqi_qflags & HAL_TXQ_CBR_DIS_BEMPTY)
384         if (qi->tqi_qflags & HAL_TXQ_CBR_DIS_QEMPTY)
390     if (qi->tqi_qflags & HAL_TXQ_BACKOFF_DISABLE)
392     if (qi->tqi_qflags & HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE)
394     if (qi->tqi_qflags & HAL_TXQ_ARB_LOCKOUT_GLOBAL)
397     else if (qi->tqi_qflags & HAL_TXQ_ARB_LOCKOUT_INTRA)
400     if (qi->tqi_qflags & HAL_TXQ_IGNORE_VIRTCOL)
403     if (qi->tqi_qflags & HAL_TXQ_SEQNUM_INC_DIS)
406     switch (qi->tqi_type) {
420                         | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
434         if (qi->tqi_readyTime) {
436               SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
488     if (qi->tqi_intFlags & HAL_TXQ_USE_LOCKOUT_BKOFF_DIS) {
509     if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE) {
514     if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE) {
519     if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE) {
524     if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE) {
529     set_tx_q_interrupts(ah, qi);