ath_hal/ar9300/ar9300_misc.c

266     u_int32_t    val;
268     val = enabled ? AR_CFG_LED_MODE_POWER_ON : AR_CFG_LED_MODE_POWER_OFF;
269     OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_POWER, val);
278     u_int32_t    val;
280     val = enabled ? AR_CFG_LED_MODE_NETWORK_ON : AR_CFG_LED_MODE_NETWORK_OFF;
281     OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_NETWORK, val);
1330     u_int32_t val[NUM_DMA_DEBUG_REGS];
1332     u_int32_t *qcu_base  = &val[0], *dcu_base = &val[4], reg;
1351         val[i] = OS_REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t)));
1352         ath_hal_printf(ah, "%d: %08x ", i, val[i]);
1360             /* only 8 QCU entries in val[0] */
1366             /* only 6 DCU entries in val[4] */
1376             val[2] & (0x7 << (i * 3)) >> (i * 3),
1383         (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22);
1386         (val[3] & 0x1c000000) >> 26, (val[6] & 0x3));
1389         (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27);
1392         (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10);
1395         (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12);
1398         (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
1731     u_int32_t val, idle_count;
1735         val = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) &
1738             (val | AR_PHY_BB_PANIC_IRQ_ENABLE) & ~AR_PHY_BB_PANIC_RST_ENABLE);
1900     u_int32_t val;
1902     val = OS_REG_READ(ah, AR_DIAG_SW);
1905     if (val & AR_DIAG_RX_CLEAR_CTL_LOW) {
1909     if (val & AR_DIAG_RX_CLEAR_EXT_LOW) {
1989      * Now get the abs val of the ppm value read in bit[0:11].
2036     u_int32_t val;
2039     val = OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY);
2042         val | AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK);
2743     u_int32_t val;
2782     val = OS_REG_READ(ah, AR_AZIMUTH_MODE);
2784         val |= AR_AZIMUTH_KEY_SEARCH_AD1 |
2788         val &= ~AR_AZIMUTH_FILTER_PASS_HOLD;
2790         val &= ~(AR_AZIMUTH_KEY_SEARCH_AD1 |
2794     OS_REG_WRITE(ah, AR_AZIMUTH_MODE, val);
2846     u_int32_t val = 0;
2857     val = OS_REG_READ(ah, AR_PHY_POWER_TX_SUB);
2860                          val & AR_PHY_POWER_TX_SUB_2_DISABLE);
2863                          val & AR_PHY_POWER_TX_SUB_3_DISABLE);
3175     int32_t val = OS_REG_READ_FIELD(ah, AR_BCN_RSSI_AVE, AR_BCN_RSSI_AVE_VAL);
3178     val = val >> 4;
3179     return val;
3828     u_int32_t val;
3845     val = OS_REG_READ(ah, AR_QMISC(qnum));
3846     OS_REG_WRITE(ah, AR_QMISC(qnum), val | AR_Q_MISC_DCU_EARLY_TERM_REQ);
3872 ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val)