ath_hal/ar9300/ar9300_misc.c

1796 ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic)
1798     bb_panic->status = AH9300(ah)->ah_bb_panic_last_status;
1809     switch (bb_panic->status) {
1817     bb_panic->tsf = ar9300_get_tsf32(ah);
1818     bb_panic->wd = MS(bb_panic->status, AR_PHY_BB_WD_STATUS);
1819     bb_panic->det = MS(bb_panic->status, AR_PHY_BB_WD_DET_HANG);
1820     bb_panic->rdar = MS(bb_panic->status, AR_PHY_BB_WD_RADAR_SM);
1821     bb_panic->r_odfm = MS(bb_panic->status, AR_PHY_BB_WD_RX_OFDM_SM);
1822     bb_panic->r_cck = MS(bb_panic->status, AR_PHY_BB_WD_RX_CCK_SM);
1823     bb_panic->t_odfm = MS(bb_panic->status, AR_PHY_BB_WD_TX_OFDM_SM);
1824     bb_panic->t_cck = MS(bb_panic->status, AR_PHY_BB_WD_TX_CCK_SM);
1825     bb_panic->agc = MS(bb_panic->status, AR_PHY_BB_WD_AGC_SM);
1826     bb_panic->src = MS(bb_panic->status, AR_PHY_BB_WD_SRCH_SM);
1827     bb_panic->phy_panic_wd_ctl1 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1);
1828     bb_panic->phy_panic_wd_ctl2 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2);
1829     bb_panic->phy_gen_ctrl = OS_REG_READ(ah, AR_PHY_GEN_CTRL);
1830     bb_panic->rxc_pcnt = bb_panic->rxf_pcnt = bb_panic->txf_pcnt = 0;
1831     bb_panic->cycles = ar9300_get_mib_cycle_counts_pct(ah,
1832                                         &bb_panic->rxc_pcnt,
1833                                         &bb_panic->rxf_pcnt,
1834                                         &bb_panic->txf_pcnt);
1838             "tsf=0x%08x ====\n", bb_panic->status, bb_panic->tsf);
1841             bb_panic->wd, bb_panic->det, bb_panic->rdar,
1842             bb_panic->r_odfm, bb_panic->r_cck, bb_panic->t_odfm,
1843             bb_panic->t_cck, bb_panic->agc, bb_panic->src);
1845             bb_panic->phy_panic_wd_ctl1, bb_panic->phy_panic_wd_ctl2);
1847             bb_panic->phy_gen_ctrl);
1848         if (bb_panic->cycles) {
1850                 "rx_frame=%d%%, tx_frame=%d%% **\n", bb_panic->rxc_pcnt,
1851                 bb_panic->rxf_pcnt, bb_panic->txf_pcnt);