Lines Matching refs:u_int32_t
104 u_int32_t numStepsInLadder;
105 u_int32_t defaultStepNum;
110 u_int32_t currStepNum;
111 u_int32_t currGain;
112 u_int32_t targetGain;
113 u_int32_t loTrig;
114 u_int32_t hiTrig;
115 u_int32_t gainFCorrection;
116 u_int32_t active;
165 u_int32_t listen_time;
166 u_int32_t ofdm_trig_high;
167 u_int32_t ofdm_trig_low;
174 u_int32_t tx_frame_count; /* Last tx_frame_count */
175 u_int32_t rx_frame_count; /* Last rx Frame count */
176 u_int32_t rx_busy_count; /* Last rx busy count */
177 u_int32_t rx_ext_busy_count; /* Last rx busy count; extension channel */
178 u_int32_t cycle_count; /* Last cycle_count (can detect wrap-around) */
179 u_int32_t ofdm_phy_err_count;/* OFDM err count since last reset */
180 u_int32_t cck_phy_err_count; /* CCK err count since last reset */
199 u_int32_t ast_ani_niup; /* ANI increased noise immunity */
200 u_int32_t ast_ani_nidown; /* ANI decreased noise immunity */
201 u_int32_t ast_ani_spurup; /* ANI increased spur immunity */
202 u_int32_t ast_ani_spurdown;/* ANI descreased spur immunity */
203 u_int32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */
204 u_int32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */
205 u_int32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */
206 u_int32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */
207 u_int32_t ast_ani_stepup; /* ANI increased first step level */
208 u_int32_t ast_ani_stepdown;/* ANI decreased first step level */
209 u_int32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */
210 u_int32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */
211 u_int32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */
212 u_int32_t ast_ani_lzero; /* ANI listen time forced to zero */
213 u_int32_t ast_ani_lneg; /* ANI listen time calculated < 0 */
222 u_int32_t rd_resetVal;
232 u_int32_t re_ts; /* 32 bit time stamp */
239 u_int32_t rq_seqNum;
240 u_int32_t rq_busy; /* 32 bit to insure atomic read/write */
261 u_int32_t ar_prev_width;
262 u_int32_t ar_phy_err_count[HAL_MAX_ACK_RADAR_DUR];
263 u_int32_t ar_ack_sum;
265 u_int32_t ar_packet_threshold; /* Thresh to determine traffic load */
266 u_int32_t ar_par_threshold; /* Thresh to determine peak */
267 u_int32_t ar_radar_rssi; /* Rssi threshold for AR event */
273 u_int32_t rs_num_radar_events; /* Number of radar events */
275 u_int32_t rs_radar_rssi; /* Thresh to start radar det (dB) */
276 u_int32_t rs_height; /* Thresh for pulse height (dB)*/
277 u_int32_t rs_pulse_rssi; /* Thresh to check if pulse is gone (dB) */
278 u_int32_t rs_inband; /* Thresh to check if pusle is inband (0.5 dB) */
312 const u_int32_t *ia_array;
313 u_int32_t ia_rows;
314 u_int32_t ia_columns;
317 (iniarray)->ia_array = (const u_int32_t *)(array); \
363 u_int32_t cal_num_samples; // Number of SW samples to collect
364 u_int32_t cal_count_max; // Number of HW samples to collect
388 u_int32_t target_rate; // rate index
389 u_int32_t reg_addr; // register offset
390 u_int32_t reg_mask; // mask of register
391 u_int32_t reg_mask_offset; // mask offset of register
392 u_int32_t sub_db; // offset value unit of dB
420 u_int32_t ah_mask_reg; /* copy of AR_IMR */
421 u_int32_t ah_mask2Reg; /* copy of AR_IMR_S2 */
422 u_int32_t ah_msi_reg; /* copy of AR_PCIE_MSI */
426 u_int32_t ah_tx_desc_mask; /* mask for TXDESC */
427 u_int32_t ah_tx_ok_interrupt_mask;
428 u_int32_t ah_tx_err_interrupt_mask;
429 u_int32_t ah_tx_desc_interrupt_mask;
430 u_int32_t ah_tx_eol_interrupt_mask;
431 u_int32_t ah_tx_urn_interrupt_mask;
435 u_int32_t ah_atim_window;
440 u_int32_t ah_beacon_rssi_threshold; /* cache beacon rssi threshold */
453 u_int32_t unsign[AR9300_MAX_CHAINS];
457 u_int32_t unsign[AR9300_MAX_CHAINS];
461 u_int32_t unsign[AR9300_MAX_CHAINS];
465 u_int32_t unsign[AR9300_MAX_CHAINS];
470 u_int32_t ah_tx6_power_in_half_dbm; /* power output for 6Mb tx */
471 u_int32_t ah_sta_id1_defaults; /* STA_ID1 default settings */
472 u_int32_t ah_misc_mode; /* MISC_MODE settings */
480 u_int32_t ah_ofdm_tx_power;
490 u_int32_t ah_gpio_mask; /* copy of enabled GPIO mask */
491 u_int32_t ah_gpio_cause; /* copy of GPIO cause (sync and async) */
495 u_int32_t ah_gpio_select; /* GPIO pin to use */
496 u_int32_t ah_polarity; /* polarity to disable RF */
497 u_int32_t ah_gpio_bit; /* after init, prev value */
516 u_int32_t ah_bt_coex_mode; /* Register setting for AR_BT_COEX_MODE */
517 u_int32_t ah_bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS]; /* Register setting for AR_BT_COEX_WEIGHT */
518 u_int32_t ah_bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS]; /* Register setting for AR_BT_COEX_WEIGHT */
519 u_int32_t ah_bt_coex_mode2; /* Register setting for AR_BT_COEX_MODE2 */
520 u_int32_t ah_bt_coex_flag; /* Special tuning flags for BT coex */
526 u_int32_t ah_avail_gen_timers; /* mask of available timers */
527 u_int32_t ah_intr_gen_timer_trigger; /* generic timer trigger interrupt state */
528 u_int32_t ah_intr_gen_timer_thresh; /* generic timer trigger interrupt state */
534 u_int32_t ah_proc_phy_err; /* Process Phy errs */
535 u_int32_t ah_ani_period; /* ani update list period */
554 u_int32_t ah_intr_txqs;
562 u_int32_t ah_cycle_count;
563 u_int32_t ah_ctl_busy;
564 u_int32_t ah_ext_busy;
583 u_int32_t ah_rifs_reg[11];
584 u_int32_t ah_rifs_sec_cnt;
587 u_int32_t original_gain[22];
592 u_int32_t ah_cycles;
593 u_int32_t ah_rx_clear;
594 u_int32_t ah_rx_frame;
595 u_int32_t ah_tx_frame;
655 u_int32_t ah_immunity_vals[6];
661 u_int32_t last_tf;
662 u_int32_t last_rf;
663 u_int32_t last_rc;
664 u_int32_t last_cc;
667 u_int32_t nf_tsf32; /* timestamp for NF calibration duration */
669 u_int32_t reg_dmn; /* Regulatory Domain */
689 u_int32_t ts_paddr_start;
690 u_int32_t ts_paddr_end;
696 u_int32_t ah_wa_reg_val; // Store the permanent value of Reg 0x4004 so we dont have to R/M/W. (We should not be reading this register when in sleep states).
704 u_int32_t pa_table[AH_MAX_CHAINS][AR9300_PAPRD_TABLE_SZ];
705 u_int32_t paprd_gain_table_entries[AR9300_PAPRD_GAIN_TABLE_SZ];
706 u_int32_t paprd_gain_table_index[AR9300_PAPRD_GAIN_TABLE_SZ];
707 u_int32_t ah_2g_paprd_rate_mask_ht20; /* Copy of eep->modal_header_2g.paprd_rate_mask_ht20 */
708 u_int32_t ah_2g_paprd_rate_mask_ht40; /* Copy of eep->modal_header_2g.paprd_rate_mask_ht40 */
709 u_int32_t ah_5g_paprd_rate_mask_ht20; /* Copy of eep->modal_header_5g.paprd_rate_mask_ht20 */
710 u_int32_t ah_5g_paprd_rate_mask_ht40; /* Copy of eep->modal_header_5g.paprd_rate_mask_ht40 */
711 u_int32_t paprd_training_power;
718 u_int32_t AR_RC;
719 u_int32_t AR_WA;
720 u_int32_t AR_PM_STATE;
721 u_int32_t AR_H_INFOL;
722 u_int32_t AR_H_INFOH;
723 u_int32_t AR_PCIE_PM_CTRL;
724 u_int32_t AR_HOST_TIMEOUT;
725 u_int32_t AR_EEPROM;
726 u_int32_t AR_SREV;
727 u_int32_t AR_INTR_SYNC_CAUSE;
728 u_int32_t AR_INTR_SYNC_CAUSE_CLR;
729 u_int32_t AR_INTR_SYNC_ENABLE;
730 u_int32_t AR_INTR_ASYNC_MASK;
731 u_int32_t AR_INTR_SYNC_MASK;
732 u_int32_t AR_INTR_ASYNC_CAUSE_CLR;
733 u_int32_t AR_INTR_ASYNC_CAUSE;
734 u_int32_t AR_INTR_ASYNC_ENABLE;
735 u_int32_t AR_PCIE_SERDES;
736 u_int32_t AR_PCIE_SERDES2;
737 u_int32_t AR_GPIO_OUT;
738 u_int32_t AR_GPIO_IN;
739 u_int32_t AR_GPIO_OE_OUT;
740 u_int32_t AR_GPIO_OE1_OUT;
741 u_int32_t AR_GPIO_INTR_POL;
742 u_int32_t AR_GPIO_INPUT_EN_VAL;
743 u_int32_t AR_GPIO_INPUT_MUX1;
744 u_int32_t AR_GPIO_INPUT_MUX2;
745 u_int32_t AR_GPIO_OUTPUT_MUX1;
746 u_int32_t AR_GPIO_OUTPUT_MUX2;
747 u_int32_t AR_GPIO_OUTPUT_MUX3;
748 u_int32_t AR_INPUT_STATE;
749 u_int32_t AR_SPARE;
750 u_int32_t AR_PCIE_CORE_RESET_EN;
751 u_int32_t AR_CLKRUN;
752 u_int32_t AR_EEPROM_STATUS_DATA;
753 u_int32_t AR_OBS;
754 u_int32_t AR_RFSILENT;
755 u_int32_t AR_GPIO_PDPU;
756 u_int32_t AR_GPIO_DS;
757 u_int32_t AR_MISC;
758 u_int32_t AR_PCIE_MSI;
759 u_int32_t AR_TSF_SNAPSHOT_BT_ACTIVE;
760 u_int32_t AR_TSF_SNAPSHOT_BT_PRIORITY;
761 u_int32_t AR_TSF_SNAPSHOT_BT_CNTL;
762 u_int32_t AR_PCIE_PHY_LATENCY_NFTS_ADJ;
763 u_int32_t AR_TDMA_CCA_CNTL;
764 u_int32_t AR_TXAPSYNC;
765 u_int32_t AR_TXSYNC_INIT_SYNC_TMR;
766 u_int32_t AR_INTR_PRIO_SYNC_CAUSE;
767 u_int32_t AR_INTR_PRIO_SYNC_ENABLE;
768 u_int32_t AR_INTR_PRIO_ASYNC_MASK;
769 u_int32_t AR_INTR_PRIO_SYNC_MASK;
770 u_int32_t AR_INTR_PRIO_ASYNC_CAUSE;
771 u_int32_t AR_INTR_PRIO_ASYNC_ENABLE;
774 u_int32_t ah_enterprise_mode;
775 u_int32_t ah_radar1;
776 u_int32_t ah_dc_offset;
779 u_int32_t ah_disable_cck;
813 u_int32_t ah_mci_int_raw;
814 u_int32_t ah_mci_int_rx_msg;
815 u_int32_t ah_mci_rx_status;
816 u_int32_t ah_mci_cont_status;
818 u_int32_t ah_mci_gpm_addr;
820 u_int32_t ah_mci_gpm_len;
821 u_int32_t ah_mci_gpm_idx;
822 u_int32_t ah_mci_sched_addr;
830 u_int32_t ah_mci_coex_wlan_channels[4];
841 u_int32_t ah_mci_wlan_cal_seq;
842 u_int32_t ah_mci_wlan_cal_done;
845 u_int32_t ah_aic_sram[ATH_AIC_MAX_BT_CHANNEL];
851 u_int32_t ah_mcast_filter_l32_set;
852 u_int32_t ah_mcast_filter_u32_set;
860 u_int32_t ah_rx_cal_chan; /* chan on which rx cal is done */
861 u_int32_t ah_rx_cal_chan_flag;
862 u_int32_t ah_rx_cal_corr[AR9300_MAX_CHAINS];
870 u_int32_t ah_ob_db1[3];
871 u_int32_t ah_db2[3];
872 u_int32_t ah_bb_panic_timeout_ms;
873 u_int32_t ah_bb_panic_last_status;
874 u_int32_t ah_tx_trig_level;
1207 u_int32_t next_beacon, u_int32_t beacon_period,
1208 u_int32_t beacon_period_fraction, HAL_OPMODE opmode);
1217 HAL_INT_MITIGATION reg, u_int32_t value);
1218 extern u_int32_t ar9300_get_intr_mitigation_timer(struct ath_hal* ah,
1220 extern u_int32_t ar9300_get_key_cache_size(struct ath_hal *);
1240 extern HAL_STATUS ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg);
1242 extern u_int32_t ar9300_ant_ctrl_common_get(struct ath_hal *ah, HAL_BOOL is_2ghz);
1245 u_int32_t *common_tbl1, u_int32_t *common_tbl2);
1250 extern HAL_BOOL ar9300_gpio_cfg_output(struct ath_hal *, u_int32_t gpio, HAL_GPIO_MUX_TYPE signalType);
1251 extern HAL_BOOL ar9300_gpio_cfg_output_led_off(struct ath_hal *, u_int32_t gpio, HAL_GPIO_MUX_TYPE signalType);
1252 extern HAL_BOOL ar9300_gpio_cfg_input(struct ath_hal *, u_int32_t gpio);
1253 extern HAL_BOOL ar9300_gpio_set(struct ath_hal *, u_int32_t gpio, u_int32_t val);
1254 extern u_int32_t ar9300_gpio_get(struct ath_hal *ah, u_int32_t gpio);
1255 extern u_int32_t ar9300_gpio_get_intr(struct ath_hal *ah);
1256 extern void ar9300_gpio_set_intr(struct ath_hal *ah, u_int, u_int32_t ilevel);
1257 extern u_int32_t ar9300_gpio_get_polarity(struct ath_hal *ah);
1258 extern void ar9300_gpio_set_polarity(struct ath_hal *ah, u_int32_t, u_int32_t);
1259 extern u_int32_t ar9300_gpio_get_mask(struct ath_hal *ah);
1260 extern int ar9300_gpio_set_mask(struct ath_hal *ah, u_int32_t mask, u_int32_t pol_map);
1266 extern u_int32_t ar9300_ppm_get_rssi_dump(struct ath_hal *);
1267 extern u_int32_t ar9300_ppm_arm_trigger(struct ath_hal *);
1269 extern u_int32_t ar9300_ppm_force(struct ath_hal *);
1271 extern u_int32_t ar9300_ppm_get_force_state(struct ath_hal *);
1272 extern void ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t);
1273 extern u_int32_t ar9300_get_dcs_mode(struct ath_hal *ah);
1274 extern u_int32_t ar9300_get_tsf32(struct ath_hal *ah);
1276 extern u_int32_t ar9300_get_tsf2_32(struct ath_hal *ah);
1280 extern u_int32_t ar9300_get_random_seed(struct ath_hal *ah);
1285 extern u_int32_t ar9300_get_cur_rssi(struct ath_hal *ah);
1286 extern u_int32_t ar9300_get_rssi_chain0(struct ath_hal *ah);
1296 extern HAL_STATUS ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration,
1297 u_int32_t next_start, HAL_QUIET_FLAG flag);
1300 u_int32_t, u_int32_t *);
1302 u_int32_t, u_int32_t, HAL_STATUS *);
1304 const void *args, u_int32_t argsize,
1305 void **result, u_int32_t *resultsize);
1325 u_int8_t *p_ath_mask, int32_t pattern_count, u_int32_t ath_pattern_len);
1326 //extern u_int32_t ar9300_wow_wake_up(struct ath_hal *ah,u_int8_t *chipPatternBytes);
1327 extern u_int32_t ar9300_wow_wake_up(struct ath_hal *ah, HAL_BOOL offloadEnable);
1328 extern bool ar9300_wow_enable(struct ath_hal *ah, u_int32_t pattern_enable, u_int32_t timeout_in_seconds, int clearbssid,
1335 u_int32_t valid;
1336 u_int32_t id;
1338 u_int32_t Flags;
1341 u_int32_t u32;
1345 u_int32_t u32;
1349 u_int32_t u32[2];
1357 u_int32_t valid;
1358 u_int32_t id;
1360 u_int32_t Flags;
1363 u_int32_t u32[4];
1367 u_int32_t u32[4];
1371 u_int32_t u32[2];
1375 u_int32_t u32[4];
1381 extern u_int32_t ar9300_wowoffload_download_rekey_data(struct ath_hal *ah, u_int32_t *data, u_int32_t size);
1382 extern void ar9300_wowoffload_retrieve_data(struct ath_hal *ah, void *buf, u_int32_t param);
1383 extern void ar9300_wowoffload_download_acer_magic(struct ath_hal *ah, HAL_BOOL valid, u_int8_t* datap, u_int32_t bytes);
1384 extern void ar9300_wowoffload_download_acer_swka(struct ath_hal *ah, u_int32_t id, HAL_BOOL valid, u_int32_t period, u_int32_t size, u_int32_t* datap);
1385 extern void ar9300_wowoffload_download_arp_info(struct ath_hal *ah, u_int32_t id, u_int32_t *data);
1386 extern void ar9300_wowoffload_download_ns_info(struct ath_hal *ah, u_int32_t id, u_int32_t *data);
1396 extern HAL_BOOL ar9300_set_reset_reg(struct ath_hal *ah, u_int32_t type);
1405 u_int8_t rxchainmask, HAL_BOOL longcal, HAL_BOOL *isIQdone, int is_scan, u_int32_t *sched_cals);
1408 HAL_BOOL *isIQdone, u_int32_t cal_type);
1416 extern HAL_BOOL ar9300_set_tx_power_limit(struct ath_hal *ah, u_int32_t limit,
1458 extern void ar9300_dump_keycache(struct ath_hal *ah, int n, u_int32_t *entry);
1478 u_int32_t dfsdomain, int *numradars, struct dfs_bin5pulse **bin5pulses,
1481 extern void ar9300_adjust_difs(struct ath_hal *ah, u_int32_t val);
1482 extern u_int32_t ar9300_dfs_config_fft(struct ath_hal *ah, HAL_BOOL is_enable);
1484 extern void ar9300_dfs_cac_war(struct ath_hal *ah, u_int32_t start);
1500 extern u_int32_t ar9300_get_spectral_config(struct ath_hal *ah);
1501 extern void ar9300_restore_spectral_config(struct ath_hal *ah, u_int32_t restoreval);
1510 extern HAL_STATUS ar9300_retrieve_capture_data(struct ath_hal *ah, u_int16_t chain_mask, int disable_dc_filter, void *sample_buf, u_int32_t *max_samples);
1525 extern u_int32_t ar9300_get_mib_cycle_counts_pct(struct ath_hal *, u_int32_t*, u_int32_t*, u_int32_t*);
1538 extern void ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type);
1539 extern void ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh);
1540 extern void ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type, u_int32_t value);
1544 extern u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg);
1545 extern u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn);
1549 extern void ar9300_start_generic_timer(struct ath_hal *ah, int index, u_int32_t timer_next,
1550 u_int32_t timer_period);
1552 extern void ar9300_get_gen_timer_interrupts(struct ath_hal *ah, u_int32_t *trigger,
1553 u_int32_t *thresh);
1564 u_int32_t rssi_threshold);
1579 extern u_int32_t ar9300_eeprom_get(struct ath_hal_9300 *ahp, EEPROM_PARAM param);
1581 extern u_int32_t ar9300_ini_fixup(struct ath_hal *ah,
1583 u_int32_t reg,
1584 u_int32_t val);
1591 extern HAL_BOOL ar9300_eeprom_set_param(struct ath_hal *ah, EEPROM_PARAM param, u_int32_t value);
1595 extern HAL_BOOL ar9300_otp_read(struct ath_hal *ah, u_int off, u_int32_t *data, HAL_BOOL is_wifi);
1650 extern void ar9300_mci_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type);
1653 extern void ar9300_mci_setup (struct ath_hal *ah, u_int32_t gpm_addr,
1655 u_int32_t sched_addr);
1660 u_int32_t flag, u_int32_t *payload, u_int8_t len,
1662 extern u_int32_t ar9300_mci_get_interrupt (struct ath_hal *ah,
1663 u_int32_t *mci_int,
1664 u_int32_t *mci_int_rx_msg);
1665 extern u_int32_t ar9300_mci_state (struct ath_hal *ah, u_int32_t state_type, u_int32_t *p_data);
1669 extern u_int32_t ar9300_mci_wait_for_gpm(struct ath_hal *ah, u_int8_t gpm_type, u_int8_t gpm_opcode, int32_t time_out);
1673 extern u_int32_t ar9300_mci_check_int (struct ath_hal *ah, u_int32_t ints);
1678 extern u_int32_t ar9300_aic_calibration (struct ath_hal *ah);
1679 extern u_int32_t ar9300_aic_start_normal (struct ath_hal *ah);
1695 extern HAL_BOOL ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val);
1700 extern void ar9300_tx99_channel_pwr_update(struct ath_hal *ah, struct ieee80211_channel *c, u_int32_t txpower);