Lines Matching refs:sc
119 struct mii_softc *sc;
122 sc = device_get_softc(dev);
131 sc->mii_capabilities = (PHY_READ(sc, MII_BMSR) | BMSR_ANEG) &
132 sc->mii_capmask;
133 if (sc->mii_capabilities & BMSR_EXTSTAT)
134 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
136 mii_phy_add_media(sc);
144 sc->mii_pdata->mii_media.ifm_mask |= IFM_FLAG0;
146 PHY_RESET(sc);
148 MIIBUS_MEDIAINIT(sc->mii_dev);
153 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
163 PHY_RESET(sc); /* XXX hardware bug work-around */
165 anar = PHY_READ(sc, RGEPHY_MII_ANAR);
176 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
179 (void)rgephy_mii_phy_auto(sc, ife->ifm_media);
201 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
220 rgephy_loop(sc);
221 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig);
222 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
223 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed);
226 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);
238 sc->mii_ticks = 0;
246 if (rgephy_linkup(sc) != 0) {
247 sc->mii_ticks = 0;
252 if (sc->mii_ticks++ == 0)
256 if (sc->mii_ticks <= sc->mii_anegticks)
259 sc->mii_ticks = 0;
260 rgephy_mii_phy_auto(sc, ife->ifm_media);
265 PHY_STATUS(sc);
272 if (sc->mii_media_active != mii->mii_media_active ||
273 sc->mii_media_status != mii->mii_media_status ||
275 rgephy_load_dspcode(sc);
277 mii_phy_update(sc, cmd);
282 rgephy_linkup(struct mii_softc *sc)
288 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 &&
289 sc->mii_mpd_rev >= RGEPHY_8211B) {
290 if (sc->mii_mpd_rev == RGEPHY_8211F) {
291 reg = PHY_READ(sc, RGEPHY_F_MII_SSR);
295 reg = PHY_READ(sc, RGEPHY_MII_SSR);
300 if (sc->mii_flags & MIIF_PHYPRIV1)
301 reg = PHY_READ(sc, URE_GMEDIASTAT);
303 reg = PHY_READ(sc, RL_GMEDIASTAT);
312 rgephy_status(struct mii_softc *sc)
314 struct mii_data *mii = sc->mii_pdata;
321 if (rgephy_linkup(sc) != 0)
324 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
325 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
343 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 &&
344 sc->mii_mpd_rev >= RGEPHY_8211B) {
345 if (sc->mii_mpd_rev == RGEPHY_8211F) {
346 ssr = PHY_READ(sc, RGEPHY_F_MII_SSR);
367 ssr = PHY_READ(sc, RGEPHY_MII_SSR);
388 if (sc->mii_flags & MIIF_PHYPRIV1)
389 bmsr = PHY_READ(sc, URE_GMEDIASTAT);
391 bmsr = PHY_READ(sc, RL_GMEDIASTAT);
407 mii->mii_media_active |= mii_phy_flowstatus(sc);
410 (PHY_READ(sc, RGEPHY_MII_1000STS) & RGEPHY_1000STS_MSR) != 0)
415 rgephy_mii_phy_auto(struct mii_softc *sc, int media)
419 rgephy_loop(sc);
420 PHY_RESET(sc);
422 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
423 if ((media & IFM_FLOW) != 0 || (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
425 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
427 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
430 PHY_WRITE(sc, RGEPHY_MII_BMCR,
438 rgephy_loop(struct mii_softc *sc)
442 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 &&
443 sc->mii_mpd_rev < RGEPHY_8211B) {
444 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
449 if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) {
451 device_printf(sc->mii_dev, "looped %d\n", i);
472 rgephy_load_dspcode(struct mii_softc *sc)
476 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8251 ||
477 sc->mii_mpd_rev >= RGEPHY_8211B)
480 PHY_WRITE(sc, 31, 0x0001);
481 PHY_WRITE(sc, 21, 0x1000);
482 PHY_WRITE(sc, 24, 0x65C7);
483 PHY_CLRBIT(sc, 4, 0x0800);
484 val = PHY_READ(sc, 4) & 0xFFF;
485 PHY_WRITE(sc, 4, val);
486 PHY_WRITE(sc, 3, 0x00A1);
487 PHY_WRITE(sc, 2, 0x0008);
488 PHY_WRITE(sc, 1, 0x1020);
489 PHY_WRITE(sc, 0, 0x1000);
490 PHY_SETBIT(sc, 4, 0x0800);
491 PHY_CLRBIT(sc, 4, 0x0800);
492 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
493 PHY_WRITE(sc, 4, val);
494 PHY_WRITE(sc, 3, 0xFF41);
495 PHY_WRITE(sc, 2, 0xDE60);
496 PHY_WRITE(sc, 1, 0x0140);
497 PHY_WRITE(sc, 0, 0x0077);
498 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
499 PHY_WRITE(sc, 4, val);
500 PHY_WRITE(sc, 3, 0xDF01);
501 PHY_WRITE(sc, 2, 0xDF20);
502 PHY_WRITE(sc, 1, 0xFF95);
503 PHY_WRITE(sc, 0, 0xFA00);
504 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
505 PHY_WRITE(sc, 4, val);
506 PHY_WRITE(sc, 3, 0xFF41);
507 PHY_WRITE(sc, 2, 0xDE20);
508 PHY_WRITE(sc, 1, 0x0140);
509 PHY_WRITE(sc, 0, 0x00BB);
510 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
511 PHY_WRITE(sc, 4, val);
512 PHY_WRITE(sc, 3, 0xDF01);
513 PHY_WRITE(sc, 2, 0xDF20);
514 PHY_WRITE(sc, 1, 0xFF95);
515 PHY_WRITE(sc, 0, 0xBF00);
516 PHY_SETBIT(sc, 4, 0x0800);
517 PHY_CLRBIT(sc, 4, 0x0800);
518 PHY_WRITE(sc, 31, 0x0000);
524 rgephy_reset(struct mii_softc *sc)
528 switch (sc->mii_mpd_rev) {
530 pcr = PHY_READ(sc, RGEPHY_F_MII_PCR1);
532 PHY_WRITE(sc, RGEPHY_F_MII_PCR1, pcr);
533 rgephy_disable_eee(sc);
536 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0) {
538 ssr = PHY_READ(sc, RGEPHY_MII_SSR);
541 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr);
546 if (sc->mii_mpd_rev >= RGEPHY_8211B) {
547 pcr = PHY_READ(sc, RGEPHY_MII_PCR);
551 PHY_WRITE(sc, RGEPHY_MII_PCR, pcr);
557 mii_phy_reset(sc);
559 rgephy_load_dspcode(sc);
563 rgephy_disable_eee(struct mii_softc *sc)
567 PHY_WRITE(sc, RGEPHY_F_EPAGSR, 0x0000);
568 PHY_WRITE(sc, MII_MMDACR, MMDACR_FN_ADDRESS |
570 PHY_WRITE(sc, MII_MMDAADR, RGEPHY_F_MMD_EEEAR);
571 PHY_WRITE(sc, MII_MMDACR, MMDACR_FN_DATANPI |
573 PHY_WRITE(sc, MII_MMDAADR, 0x0000);
574 PHY_WRITE(sc, MII_MMDACR, 0x0000);
580 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
581 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
582 PHY_WRITE(sc, RGEPHY_MII_1000CTL, RGEPHY_1000CTL_AHD |
584 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_RESET |