Lines Matching defs:sc
193 static void rl_init_locked(struct rl_softc *sc);
268 CSR_WRITE_1(sc, RL_EECMD, \
269 CSR_READ_1(sc, RL_EECMD) | x)
272 CSR_WRITE_1(sc, RL_EECMD, \
273 CSR_READ_1(sc, RL_EECMD) & ~x)
279 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
283 d = addr | sc->rl_eecmd_read;
306 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
312 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
317 rl_eeprom_putbyte(sc, addr);
319 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
327 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
334 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
343 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
349 rl_eeprom_getword(sc, off + i, &word);
364 struct rl_softc *sc;
367 sc = device_get_softc(dev);
369 val = CSR_READ_1(sc, RL_MII);
370 CSR_BARRIER(sc, RL_MII, 1,
382 struct rl_softc *sc;
384 sc = device_get_softc(dev);
386 CSR_WRITE_1(sc, RL_MII, val);
387 CSR_BARRIER(sc, RL_MII, 1,
394 struct rl_softc *sc;
397 sc = device_get_softc(dev);
399 if (sc->rl_type == RL_8139) {
426 return (CSR_READ_1(sc, RL_MEDIASTAT));
428 device_printf(sc->rl_dev, "bad phy register\n");
431 return (CSR_READ_2(sc, rl8139_reg));
440 struct rl_softc *sc;
443 sc = device_get_softc(dev);
445 if (sc->rl_type == RL_8139) {
467 device_printf(sc->rl_dev, "bad phy register\n");
470 CSR_WRITE_2(sc, rl8139_reg, data);
482 struct rl_softc *sc;
486 sc = device_get_softc(dev);
487 mii = device_get_softc(sc->rl_miibus);
488 ifp = sc->rl_ifp;
493 sc->rl_flags &= ~RL_FLAG_LINK;
499 sc->rl_flags |= RL_FLAG_LINK;
516 rl_rxfilter(struct rl_softc *sc)
518 struct ifnet *ifp = sc->rl_ifp;
524 RL_LOCK_ASSERT(sc);
526 rxfilt = CSR_READ_4(sc, RL_RXCFG);
558 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
559 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
560 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
564 rl_reset(struct rl_softc *sc)
568 RL_LOCK_ASSERT(sc);
570 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
574 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
578 device_printf(sc->rl_dev, "reset never completed!\n");
641 struct rl_softc *sc;
650 sc = device_get_softc(dev);
652 sc->rl_dev = dev;
654 sc->rl_twister_enable = 0;
656 TUNABLE_INT_FETCH(tn, &sc->rl_twister_enable);
657 ctx = device_get_sysctl_ctx(sc->rl_dev);
658 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
660 &sc->rl_twister_enable, 0, "");
662 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
664 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
682 sc->rl_res_id = PCIR_BAR(0);
683 sc->rl_res_type = SYS_RES_IOPORT;
684 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
685 &sc->rl_res_id, RF_ACTIVE);
687 if (prefer_iomap == 0 || sc->rl_res == NULL) {
688 sc->rl_res_id = PCIR_BAR(1);
689 sc->rl_res_type = SYS_RES_MEMORY;
690 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
691 &sc->rl_res_id, RF_ACTIVE);
693 if (sc->rl_res == NULL) {
706 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
711 sc->rl_btag = rman_get_bustag(sc->rl_res);
712 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
716 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
719 if (sc->rl_irq[0] == NULL) {
725 sc->rl_cfg0 = RL_8139_CFG0;
726 sc->rl_cfg1 = RL_8139_CFG1;
727 sc->rl_cfg2 = 0;
728 sc->rl_cfg3 = RL_8139_CFG3;
729 sc->rl_cfg4 = RL_8139_CFG4;
730 sc->rl_cfg5 = RL_8139_CFG5;
736 RL_LOCK(sc);
737 rl_reset(sc);
738 RL_UNLOCK(sc);
740 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
741 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
743 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
748 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
758 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
761 sc->rl_type = 0;
764 sc->rl_type = t->rl_basetype;
770 if (sc->rl_type == 0) {
773 sc->rl_type = RL_8139;
779 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
782 if ((error = rl_dma_alloc(sc)) != 0)
785 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
796 if (sc->rl_type == RL_8139)
798 error = mii_attach(dev, &sc->rl_miibus, ifp, rl_ifmedia_upd,
805 ifp->if_softc = sc;
814 if (sc->rl_type == RL_8139 &&
815 pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
816 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
826 rl_clrwol(sc);
847 error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE,
848 NULL, rl_intr, sc, &sc->rl_intrhand[0]);
850 device_printf(sc->rl_dev, "couldn't set up irq\n");
871 struct rl_softc *sc;
874 sc = device_get_softc(dev);
875 ifp = sc->rl_ifp;
877 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
885 RL_LOCK(sc);
886 rl_stop(sc);
887 RL_UNLOCK(sc);
888 callout_drain(&sc->rl_stat_callout);
892 sc->suspended = 1;
894 if (sc->rl_miibus)
895 device_delete_child(dev, sc->rl_miibus);
898 if (sc->rl_intrhand[0])
899 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
900 if (sc->rl_irq[0])
901 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]);
902 if (sc->rl_res)
903 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
904 sc->rl_res);
909 rl_dma_free(sc);
911 mtx_destroy(&sc->rl_mtx);
917 rl_dma_alloc(struct rl_softc *sc)
925 error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev), /* parent */
934 &sc->rl_parent_tag);
936 device_printf(sc->rl_dev,
941 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
950 &sc->rl_cdata.rl_rx_tag);
952 device_printf(sc->rl_dev,
957 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
966 &sc->rl_cdata.rl_tx_tag);
968 device_printf(sc->rl_dev, "failed to create Tx DMA tag.\n");
975 error = bus_dmamem_alloc(sc->rl_cdata.rl_rx_tag,
976 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_WAITOK |
977 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->rl_cdata.rl_rx_dmamap);
979 device_printf(sc->rl_dev,
984 error = bus_dmamap_load(sc->rl_cdata.rl_rx_tag,
985 sc->rl_cdata.rl_rx_dmamap, sc->rl_cdata.rl_rx_buf,
989 device_printf(sc->rl_dev,
993 sc->rl_cdata.rl_rx_buf_paddr = ctx.rl_busaddr;
997 sc->rl_cdata.rl_tx_chain[i] = NULL;
998 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
999 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 0,
1000 &sc->rl_cdata.rl_tx_dmamap[i]);
1002 device_printf(sc->rl_dev,
1009 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1010 sc->rl_cdata.rl_rx_buf += RL_RX_8139_BUF_RESERVE;
1017 rl_dma_free(struct rl_softc *sc)
1022 if (sc->rl_cdata.rl_rx_tag != NULL) {
1023 if (sc->rl_cdata.rl_rx_buf_paddr != 0)
1024 bus_dmamap_unload(sc->rl_cdata.rl_rx_tag,
1025 sc->rl_cdata.rl_rx_dmamap);
1026 if (sc->rl_cdata.rl_rx_buf_ptr != NULL)
1027 bus_dmamem_free(sc->rl_cdata.rl_rx_tag,
1028 sc->rl_cdata.rl_rx_buf_ptr,
1029 sc->rl_cdata.rl_rx_dmamap);
1030 sc->rl_cdata.rl_rx_buf_ptr = NULL;
1031 sc->rl_cdata.rl_rx_buf = NULL;
1032 sc->rl_cdata.rl_rx_buf_paddr = 0;
1033 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag);
1034 sc->rl_cdata.rl_tx_tag = NULL;
1038 if (sc->rl_cdata.rl_tx_tag != NULL) {
1040 if (sc->rl_cdata.rl_tx_dmamap[i] != NULL) {
1042 sc->rl_cdata.rl_tx_tag,
1043 sc->rl_cdata.rl_tx_dmamap[i]);
1044 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
1047 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag);
1048 sc->rl_cdata.rl_tx_tag = NULL;
1051 if (sc->rl_parent_tag != NULL) {
1052 bus_dma_tag_destroy(sc->rl_parent_tag);
1053 sc->rl_parent_tag = NULL;
1061 rl_list_tx_init(struct rl_softc *sc)
1066 RL_LOCK_ASSERT(sc);
1068 cd = &sc->rl_cdata;
1071 CSR_WRITE_4(sc,
1075 sc->rl_cdata.cur_tx = 0;
1076 sc->rl_cdata.last_tx = 0;
1082 rl_list_rx_init(struct rl_softc *sc)
1085 RL_LOCK_ASSERT(sc);
1087 bzero(sc->rl_cdata.rl_rx_buf_ptr,
1089 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, sc->rl_cdata.rl_rx_dmamap,
1117 rl_rxeof(struct rl_softc *sc)
1120 struct ifnet *ifp = sc->rl_ifp;
1130 RL_LOCK_ASSERT(sc);
1132 bus_dmamap_sync(sc->rl_cdata.rl_rx_tag, sc->rl_cdata.rl_rx_dmamap,
1135 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1138 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1145 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1148 if (sc->rxcycles <= 0)
1150 sc->rxcycles--;
1153 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1173 rl_init_locked(sc);
1196 rxbufpos = sc->rl_cdata.rl_rx_buf +
1198 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1199 rxbufpos = sc->rl_cdata.rl_rx_buf;
1201 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1207 sc->rl_cdata.rl_rx_buf);
1217 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1225 RL_UNLOCK(sc);
1227 RL_LOCK(sc);
1240 rl_txeof(struct rl_softc *sc)
1242 struct ifnet *ifp = sc->rl_ifp;
1245 RL_LOCK_ASSERT(sc);
1252 if (RL_LAST_TXMBUF(sc) == NULL)
1254 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1261 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc),
1263 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc));
1264 m_freem(RL_LAST_TXMBUF(sc));
1265 RL_LAST_TXMBUF(sc) = NULL;
1272 (sc->rl_txthresh < 2016))
1273 sc->rl_txthresh += 32;
1281 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1282 oldthresh = sc->rl_txthresh;
1285 rl_init_locked(sc);
1287 sc->rl_txthresh = oldthresh;
1290 RL_INC(sc->rl_cdata.last_tx);
1292 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1294 if (RL_LAST_TXMBUF(sc) == NULL)
1295 sc->rl_watchdog_timer = 0;
1299 rl_twister_update(struct rl_softc *sc)
1319 switch (sc->rl_twister)
1327 if (CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_LINK_OK) {
1328 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD);
1329 sc->rl_twister = FIND_ROW;
1331 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD);
1332 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
1333 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
1334 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
1335 sc->rl_twister = DONE;
1343 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
1345 sc->rl_twist_row = 3;
1347 sc->rl_twist_row = 2;
1349 sc->rl_twist_row = 1;
1351 sc->rl_twist_row = 0;
1352 sc->rl_twist_col = 0;
1353 sc->rl_twister = SET_PARAM;
1356 if (sc->rl_twist_col == 0)
1357 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
1358 CSR_WRITE_4(sc, RL_PARA7C,
1359 param[sc->rl_twist_row][sc->rl_twist_col]);
1360 if (++sc->rl_twist_col == 4) {
1361 if (sc->rl_twist_row == 3)
1362 sc->rl_twister = RECHK_LONG;
1364 sc->rl_twister = DONE;
1372 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
1374 sc->rl_twister = DONE;
1376 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_RETUNE);
1377 sc->rl_twister = RETUNE;
1382 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
1383 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
1384 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
1385 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
1386 sc->rl_twist_row--;
1387 sc->rl_twist_col = 0;
1388 sc->rl_twister = SET_PARAM;
1400 struct rl_softc *sc = xsc;
1404 RL_LOCK_ASSERT(sc);
1416 mii = device_get_softc(sc->rl_miibus);
1418 if ((sc->rl_flags & RL_FLAG_LINK) == 0)
1419 rl_miibus_statchg(sc->rl_dev);
1420 if (sc->rl_twister_enable) {
1421 if (sc->rl_twister == DONE)
1422 rl_watchdog(sc);
1424 rl_twister_update(sc);
1425 if (sc->rl_twister == DONE)
1430 rl_watchdog(sc);
1434 callout_reset(&sc->rl_stat_callout, _ticks, rl_tick, sc);
1441 struct rl_softc *sc = ifp->if_softc;
1444 RL_LOCK(sc);
1447 RL_UNLOCK(sc);
1454 struct rl_softc *sc = ifp->if_softc;
1457 RL_LOCK_ASSERT(sc);
1459 sc->rxcycles = count;
1460 rx_npkts = rl_rxeof(sc);
1461 rl_txeof(sc);
1470 status = CSR_READ_2(sc, RL_ISR);
1474 CSR_WRITE_2(sc, RL_ISR, status);
1480 rl_init_locked(sc);
1490 struct rl_softc *sc = arg;
1491 struct ifnet *ifp = sc->rl_ifp;
1495 RL_LOCK(sc);
1497 if (sc->suspended)
1507 status = CSR_READ_2(sc, RL_ISR);
1513 CSR_WRITE_2(sc, RL_IMR, 0);
1515 CSR_WRITE_2(sc, RL_ISR, status);
1518 rl_rxeof(sc);
1520 rl_txeof(sc);
1523 rl_init_locked(sc);
1524 RL_UNLOCK(sc);
1528 status = CSR_READ_2(sc, RL_ISR);
1539 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1541 RL_UNLOCK(sc);
1549 rl_encap(struct rl_softc *sc, struct mbuf **m_head)
1555 RL_LOCK_ASSERT(sc);
1593 error = bus_dmamap_load_mbuf_sg(sc->rl_cdata.rl_tx_tag,
1594 RL_CUR_DMAMAP(sc), m, txsegs, &nsegs, 0);
1603 RL_CUR_TXMBUF(sc) = m;
1604 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc),
1606 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), RL_ADDR_LO(txsegs[0].ds_addr));
1617 struct rl_softc *sc = ifp->if_softc;
1619 RL_LOCK(sc);
1621 RL_UNLOCK(sc);
1627 struct rl_softc *sc = ifp->if_softc;
1630 RL_LOCK_ASSERT(sc);
1633 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
1636 while (RL_CUR_TXMBUF(sc) == NULL) {
1643 if (rl_encap(sc, &m_head)) {
1652 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1655 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1656 RL_TXTHRESH(sc->rl_txthresh) |
1657 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1659 RL_INC(sc->rl_cdata.cur_tx);
1662 sc->rl_watchdog_timer = 5;
1670 if (RL_CUR_TXMBUF(sc) != NULL)
1677 struct rl_softc *sc = xsc;
1679 RL_LOCK(sc);
1680 rl_init_locked(sc);
1681 RL_UNLOCK(sc);
1685 rl_init_locked(struct rl_softc *sc)
1687 struct ifnet *ifp = sc->rl_ifp;
1691 RL_LOCK_ASSERT(sc);
1693 mii = device_get_softc(sc->rl_miibus);
1701 rl_stop(sc);
1703 rl_reset(sc);
1704 if (sc->rl_twister_enable) {
1711 sc->rl_twister = CHK_LINK;
1719 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1721 bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN);
1722 CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]);
1723 CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]);
1724 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1727 CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr +
1730 rl_list_tx_init(sc);
1732 rl_list_rx_init(sc);
1737 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1742 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1743 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1746 rl_rxfilter(sc);
1751 CSR_WRITE_2(sc, RL_IMR, 0);
1755 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1758 sc->rl_txthresh = RL_TX_THRESH_INIT;
1761 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1764 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1766 sc->rl_flags &= ~RL_FLAG_LINK;
1769 CSR_WRITE_1(sc, sc->rl_cfg1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1774 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1783 struct rl_softc *sc = ifp->if_softc;
1786 mii = device_get_softc(sc->rl_miibus);
1788 RL_LOCK(sc);
1790 RL_UNLOCK(sc);
1801 struct rl_softc *sc = ifp->if_softc;
1804 mii = device_get_softc(sc->rl_miibus);
1806 RL_LOCK(sc);
1810 RL_UNLOCK(sc);
1818 struct rl_softc *sc = ifp->if_softc;
1823 RL_LOCK(sc);
1826 ((ifp->if_flags ^ sc->rl_if_flags) &
1828 rl_rxfilter(sc);
1830 rl_init_locked(sc);
1832 rl_stop(sc);
1833 sc->rl_if_flags = ifp->if_flags;
1834 RL_UNLOCK(sc);
1838 RL_LOCK(sc);
1839 rl_rxfilter(sc);
1840 RL_UNLOCK(sc);
1844 mii = device_get_softc(sc->rl_miibus);
1855 RL_LOCK(sc);
1857 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1859 RL_UNLOCK(sc);
1867 RL_LOCK(sc);
1868 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1870 RL_UNLOCK(sc);
1893 rl_watchdog(struct rl_softc *sc)
1896 RL_LOCK_ASSERT(sc);
1898 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0)
1901 device_printf(sc->rl_dev, "watchdog timeout\n");
1902 if_inc_counter(sc->rl_ifp, IFCOUNTER_OERRORS, 1);
1904 rl_txeof(sc);
1905 rl_rxeof(sc);
1906 sc->rl_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1907 rl_init_locked(sc);
1915 rl_stop(struct rl_softc *sc)
1918 struct ifnet *ifp = sc->rl_ifp;
1920 RL_LOCK_ASSERT(sc);
1922 sc->rl_watchdog_timer = 0;
1923 callout_stop(&sc->rl_stat_callout);
1925 sc->rl_flags &= ~RL_FLAG_LINK;
1927 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1928 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1931 if ((CSR_READ_1(sc, RL_COMMAND) &
1936 device_printf(sc->rl_dev, "Unable to stop Tx/Rx MAC\n");
1942 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1943 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag,
1944 sc->rl_cdata.rl_tx_dmamap[i],
1946 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag,
1947 sc->rl_cdata.rl_tx_dmamap[i]);
1948 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1949 sc->rl_cdata.rl_tx_chain[i] = NULL;
1950 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1964 struct rl_softc *sc;
1966 sc = device_get_softc(dev);
1968 RL_LOCK(sc);
1969 rl_stop(sc);
1970 rl_setwol(sc);
1971 sc->suspended = 1;
1972 RL_UNLOCK(sc);
1985 struct rl_softc *sc;
1990 sc = device_get_softc(dev);
1991 ifp = sc->rl_ifp;
1993 RL_LOCK(sc);
1996 pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
1998 pmstat = pci_read_config(sc->rl_dev,
2002 pci_write_config(sc->rl_dev,
2009 rl_clrwol(sc);
2014 rl_init_locked(sc);
2016 sc->suspended = 0;
2018 RL_UNLOCK(sc);
2030 struct rl_softc *sc;
2032 sc = device_get_softc(dev);
2034 RL_LOCK(sc);
2035 rl_stop(sc);
2041 sc->rl_ifp->if_flags &= ~IFF_UP;
2042 rl_setwol(sc);
2043 RL_UNLOCK(sc);
2049 rl_setwol(struct rl_softc *sc)
2056 RL_LOCK_ASSERT(sc);
2058 ifp = sc->rl_ifp;
2061 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
2065 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
2068 v = CSR_READ_1(sc, sc->rl_cfg1);
2072 CSR_WRITE_1(sc, sc->rl_cfg1, v);
2074 v = CSR_READ_1(sc, sc->rl_cfg3);
2078 CSR_WRITE_1(sc, sc->rl_cfg3, v);
2080 v = CSR_READ_1(sc, sc->rl_cfg5);
2089 CSR_WRITE_1(sc, sc->rl_cfg5, v);
2092 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2095 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
2099 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
2103 rl_clrwol(struct rl_softc *sc)
2108 ifp = sc->rl_ifp;
2113 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
2115 v = CSR_READ_1(sc, sc->rl_cfg3);
2117 CSR_WRITE_1(sc, sc->rl_cfg3, v);
2120 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2122 v = CSR_READ_1(sc, sc->rl_cfg5);
2125 CSR_WRITE_1(sc, sc->rl_cfg5, v);