Lines Matching refs:phy
73 struct e1000_phy_info *phy = &hw->phy;
77 phy->ops.init_params = e1000_null_ops_generic;
78 phy->ops.acquire = e1000_null_ops_generic;
79 phy->ops.check_polarity = e1000_null_ops_generic;
80 phy->ops.check_reset_block = e1000_null_ops_generic;
81 phy->ops.commit = e1000_null_ops_generic;
82 phy->ops.force_speed_duplex = e1000_null_ops_generic;
83 phy->ops.get_cfg_done = e1000_null_ops_generic;
84 phy->ops.get_cable_length = e1000_null_ops_generic;
85 phy->ops.get_info = e1000_null_ops_generic;
86 phy->ops.set_page = e1000_null_set_page;
87 phy->ops.read_reg = e1000_null_read_reg;
88 phy->ops.read_reg_locked = e1000_null_read_reg;
89 phy->ops.read_reg_page = e1000_null_read_reg;
90 phy->ops.release = e1000_null_phy_generic;
91 phy->ops.reset = e1000_null_ops_generic;
92 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
93 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
94 phy->ops.write_reg = e1000_null_write_reg;
95 phy->ops.write_reg_locked = e1000_null_write_reg;
96 phy->ops.write_reg_page = e1000_null_write_reg;
97 phy->ops.power_up = e1000_null_phy_generic;
98 phy->ops.power_down = e1000_null_phy_generic;
99 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
100 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
101 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
227 struct e1000_phy_info *phy = &hw->phy;
234 if (!phy->ops.read_reg)
238 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
242 phy->id = (u32)(phy_id << 16);
244 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
248 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
249 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
251 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
272 if (!hw->phy.ops.write_reg)
275 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
279 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
293 struct e1000_phy_info *phy = &hw->phy;
308 (phy->addr << E1000_MDIC_PHY_SHIFT) |
358 struct e1000_phy_info *phy = &hw->phy;
374 (phy->addr << E1000_MDIC_PHY_SHIFT) |
424 struct e1000_phy_info *phy = &hw->phy;
434 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
471 struct e1000_phy_info *phy = &hw->phy;
478 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
480 hw->phy.addr);
492 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
661 if (!hw->phy.ops.acquire)
664 ret_val = hw->phy.ops.acquire(hw);
671 hw->phy.ops.release(hw);
691 if (!hw->phy.ops.acquire)
694 ret_val = hw->phy.ops.acquire(hw);
701 hw->phy.ops.release(hw);
712 * already acquired. Note, this function sets phy.addr to 1 so the caller
721 hw->phy.addr = 1;
745 if (!hw->phy.ops.acquire)
748 ret_val = hw->phy.ops.acquire(hw);
762 hw->phy.ops.release(hw);
814 if (!hw->phy.ops.acquire)
817 ret_val = hw->phy.ops.acquire(hw);
831 hw->phy.ops.release(hw);
885 if (!hw->phy.ops.acquire)
888 ret_val = hw->phy.ops.acquire(hw);
904 hw->phy.ops.release(hw);
960 if (!hw->phy.ops.acquire)
963 ret_val = hw->phy.ops.acquire(hw);
976 hw->phy.ops.release(hw);
1021 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1026 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1031 switch (hw->phy.ms_type) {
1046 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1062 if (hw->phy.type == e1000_phy_82580) {
1063 ret_val = hw->phy.ops.reset(hw);
1071 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1080 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1085 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1094 switch (hw->phy.mdix) {
1106 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1122 struct e1000_phy_info *phy = &hw->phy;
1130 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1135 if (phy->type != e1000_phy_bm)
1147 switch (phy->mdix) {
1171 if (phy->disable_polarity_correction)
1175 if (phy->type == e1000_phy_bm) {
1177 if (phy->id == BME1000_E_PHY_ID_R2) {
1179 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1184 ret_val = phy->ops.commit(hw);
1194 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1198 if ((phy->type == e1000_phy_m88) &&
1199 (phy->revision < E1000_REVISION_4) &&
1200 (phy->id != BME1000_E_PHY_ID_R2)) {
1204 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1211 if ((phy->revision == E1000_REVISION_2) &&
1212 (phy->id == M88E1111_I_PHY_ID)) {
1223 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1229 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1231 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1236 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1242 ret_val = phy->ops.commit(hw);
1248 if (phy->type == e1000_phy_82578) {
1249 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1257 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1275 struct e1000_phy_info *phy = &hw->phy;
1283 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1296 switch (phy->mdix) {
1305 if (phy->id != M88E1112_E_PHY_ID) {
1324 if (phy->disable_polarity_correction)
1328 if (phy->id == M88E1543_E_PHY_ID) {
1331 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1335 ret_val = phy->ops.commit(hw);
1346 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1351 ret_val = phy->ops.commit(hw);
1373 struct e1000_phy_info *phy = &hw->phy;
1380 ret_val = hw->phy.ops.reset(hw);
1394 if (phy->type == e1000_phy_igp) {
1396 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
1404 if (hw->phy.ops.set_d0_lplu_state) {
1405 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
1412 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1418 switch (phy->mdix) {
1431 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1441 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1443 ret_val = phy->ops.read_reg(hw,
1450 ret_val = phy->ops.write_reg(hw,
1457 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1462 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1484 struct e1000_phy_info *phy = &hw->phy;
1491 phy->autoneg_advertised &= phy->autoneg_mask;
1494 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1498 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1500 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1523 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1526 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1532 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1538 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1544 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1550 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1554 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1613 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1619 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1620 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1637 struct e1000_phy_info *phy = &hw->phy;
1646 phy->autoneg_advertised &= phy->autoneg_mask;
1651 if (!phy->autoneg_advertised)
1652 phy->autoneg_advertised = phy->autoneg_mask;
1665 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1670 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1677 if (phy->autoneg_wait_to_complete) {
1718 ret_val = hw->phy.ops.force_speed_duplex(hw);
1754 struct e1000_phy_info *phy = &hw->phy;
1761 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1767 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1774 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1781 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1789 if (phy->autoneg_wait_to_complete) {
1790 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1820 struct e1000_phy_info *phy = &hw->phy;
1828 if (phy->type != e1000_phy_i210) {
1832 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1838 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1846 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1852 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1856 /* Reset the phy to commit changes. */
1857 ret_val = hw->phy.ops.commit(hw);
1861 if (phy->autoneg_wait_to_complete) {
1862 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1872 switch (hw->phy.id) {
1882 if (hw->phy.type != e1000_phy_m88)
1893 ret_val = phy->ops.write_reg(hw,
1911 if (hw->phy.type != e1000_phy_m88)
1914 if (hw->phy.id == I347AT4_E_PHY_ID ||
1915 hw->phy.id == M88E1340M_E_PHY_ID ||
1916 hw->phy.id == M88E1112_E_PHY_ID)
1918 if (hw->phy.id == I210_I_PHY_ID)
1920 if ((hw->phy.id == M88E1543_E_PHY_ID) ||
1921 (hw->phy.id == M88E1512_E_PHY_ID))
1923 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1927 /* Resetting the phy means we need to re-force TX_CLK in the
1932 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1939 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1944 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1959 struct e1000_phy_info *phy = &hw->phy;
1966 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1972 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1977 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1984 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1992 if (phy->autoneg_wait_to_complete) {
1993 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
2043 /* Disable autoneg on the phy */
2090 struct e1000_phy_info *phy = &hw->phy;
2096 if (!hw->phy.ops.read_reg)
2099 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2105 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2114 if (phy->smart_speed == e1000_smart_speed_on) {
2115 ret_val = phy->ops.read_reg(hw,
2122 ret_val = phy->ops.write_reg(hw,
2127 } else if (phy->smart_speed == e1000_smart_speed_off) {
2128 ret_val = phy->ops.read_reg(hw,
2135 ret_val = phy->ops.write_reg(hw,
2141 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2142 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2143 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2145 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2151 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2157 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2174 struct e1000_phy_info *phy = &hw->phy;
2180 switch (phy->type) {
2197 phy->speed_downgraded = false;
2201 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2204 phy->speed_downgraded = !!(phy_data & mask);
2219 struct e1000_phy_info *phy = &hw->phy;
2225 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2228 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
2246 struct e1000_phy_info *phy = &hw->phy;
2255 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2271 ret_val = phy->ops.read_reg(hw, offset, &data);
2274 phy->cable_polarity = ((data & mask)
2289 struct e1000_phy_info *phy = &hw->phy;
2297 if (phy->polarity_correction) {
2305 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2308 phy->cable_polarity = ((phy_data & mask)
2329 if (!hw->phy.ops.read_reg)
2334 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2337 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2368 if (!hw->phy.ops.read_reg)
2376 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2387 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2420 struct e1000_phy_info *phy = &hw->phy;
2426 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2436 phy->min_cable_length = e1000_m88_cable_length_table[index];
2437 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2439 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2446 struct e1000_phy_info *phy = &hw->phy;
2453 switch (hw->phy.id) {
2456 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2457 (I347AT4_PCDL + phy->addr),
2463 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2470 /* Populate the phy structure with cable length in meters */
2471 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2472 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2473 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2480 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2485 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2490 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2496 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2502 /* Populate the phy structure with cable length in meters */
2503 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2504 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2505 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2508 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2516 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2521 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2525 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2536 phy->min_cable_length = e1000_m88_cable_length_table[index];
2537 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2539 phy->cable_length = (phy->min_cable_length +
2540 phy->max_cable_length) / 2;
2543 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2569 struct e1000_phy_info *phy = &hw->phy;
2585 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2618 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2620 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2622 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2639 struct e1000_phy_info *phy = &hw->phy;
2646 if (phy->media_type != e1000_media_type_copper) {
2660 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2664 phy->polarity_correction = !!(phy_data &
2671 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2675 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2678 ret_val = hw->phy.ops.get_cable_length(hw);
2682 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2686 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2690 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2695 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2696 phy->local_rx = e1000_1000t_rx_status_undefined;
2697 phy->remote_rx = e1000_1000t_rx_status_undefined;
2714 struct e1000_phy_info *phy = &hw->phy;
2730 phy->polarity_correction = true;
2736 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2740 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2744 ret_val = phy->ops.get_cable_length(hw);
2748 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2752 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2756 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2760 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2761 phy->local_rx = e1000_1000t_rx_status_undefined;
2762 phy->remote_rx = e1000_1000t_rx_status_undefined;
2772 * Populates "phy" structure with various feature states.
2776 struct e1000_phy_info *phy = &hw->phy;
2792 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2795 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2797 if (phy->polarity_correction) {
2803 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2808 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2812 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2815 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2816 phy->local_rx = e1000_1000t_rx_status_undefined;
2817 phy->remote_rx = e1000_1000t_rx_status_undefined;
2836 if (!hw->phy.ops.read_reg)
2839 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2844 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2864 struct e1000_phy_info *phy = &hw->phy;
2870 if (phy->ops.check_reset_block) {
2871 ret_val = phy->ops.check_reset_block(hw);
2876 ret_val = phy->ops.acquire(hw);
2884 usec_delay(phy->reset_delay_us);
2891 phy->ops.release(hw);
2893 return phy->ops.get_cfg_done(hw);
2924 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2926 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2928 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2930 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2932 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2934 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2936 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2938 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2940 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2942 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2944 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2946 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2948 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2950 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2952 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2954 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2956 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2958 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2960 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2962 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2964 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2966 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2968 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2970 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2972 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2974 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2978 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2980 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2984 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2986 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2988 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2990 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2997 * @phy_id: phy_id read from the phy
2999 * Returns the phy type from the id.
3074 hw->phy.id = phy_type;
3077 hw->phy.addr = phy_addr;
3082 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3103 * Returns the phy address for the page requested.
3131 ret_val = hw->phy.ops.acquire(hw);
3142 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3147 /* Page select is register 31 for phy address 1 and 22 for
3148 * phy address 2 and 3. Page select is shifted only for
3149 * phy address 1.
3151 if (hw->phy.addr == 1) {
3170 hw->phy.ops.release(hw);
3191 ret_val = hw->phy.ops.acquire(hw);
3202 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3207 /* Page select is register 31 for phy address 1 and 22 for
3208 * phy address 2 and 3. Page select is shifted only for
3209 * phy address 1.
3211 if (hw->phy.addr == 1) {
3229 hw->phy.ops.release(hw);
3250 ret_val = hw->phy.ops.acquire(hw);
3261 hw->phy.addr = 1;
3275 hw->phy.ops.release(hw);
3295 ret_val = hw->phy.ops.acquire(hw);
3306 hw->phy.addr = 1;
3321 hw->phy.ops.release(hw);
3343 /* All page select, port ctrl and wakeup registers use phy address 1 */
3344 hw->phy.addr = 1;
3509 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3511 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3527 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3529 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3551 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3556 ret_val = hw->phy.ops.acquire(hw);
3582 hw->phy.addr = phy_addr;
3596 hw->phy.ops.release(hw);
3661 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3666 ret_val = hw->phy.ops.acquire(hw);
3690 if ((hw->phy.type == e1000_phy_82578) &&
3691 (hw->phy.revision >= 1) &&
3692 (hw->phy.addr == 2) &&
3708 hw->phy.addr = phy_addr;
3723 hw->phy.ops.release(hw);
3805 /* This takes care of the difference with desktop vs mobile phy */
3806 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3810 /* All operations in this function are phy address 2 */
3811 hw->phy.addr = 2;
3850 if (hw->phy.type != e1000_phy_82578)
3854 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3859 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3873 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3879 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3893 struct e1000_phy_info *phy = &hw->phy;
3899 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3902 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3917 struct e1000_phy_info *phy = &hw->phy;
3924 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3930 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3936 if (phy->autoneg_wait_to_complete) {
3937 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3966 struct e1000_phy_info *phy = &hw->phy;
3982 phy->polarity_correction = true;
3988 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3992 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3996 ret_val = hw->phy.ops.get_cable_length(hw);
4000 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
4004 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
4008 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
4012 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
4013 phy->local_rx = e1000_1000t_rx_status_undefined;
4014 phy->remote_rx = e1000_1000t_rx_status_undefined;
4029 struct e1000_phy_info *phy = &hw->phy;
4035 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4045 phy->cable_length = length;
4067 ret_val = hw->phy.ops.acquire(hw);
4077 hw->phy.ops.release(hw);
4099 ret_val = hw->phy.ops.acquire(hw);
4109 hw->phy.ops.release(hw);
4263 DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n");
4283 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);
4287 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address);
4291 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA |
4297 ret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data);
4299 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data);
4304 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0);