dev/e1000/e1000_mac.c

190 	s32 ret_val = E1000_SUCCESS;
229 	return ret_val;
244 	s32 ret_val;
251 	ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
253 	if (ret_val) {
411 	s32 ret_val;
417 	ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
418 	if (ret_val)
419 		return ret_val;
431 	ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
433 	if (ret_val) {
435 		return ret_val;
452 		ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
453 		if (ret_val) {
455 			return ret_val;
720 	s32 ret_val;
737 	ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
738 	if (ret_val)
739 		return ret_val;
768 	ret_val = e1000_config_fc_after_link_up_generic(hw);
769 	if (ret_val)
772 	return ret_val;
788 	s32 ret_val;
821 		ret_val = e1000_config_fc_after_link_up_generic(hw);
822 		if (ret_val) {
824 			return ret_val;
855 	s32 ret_val;
886 		ret_val = e1000_config_fc_after_link_up_generic(hw);
887 		if (ret_val) {
889 			return ret_val;
957 	s32 ret_val;
973 		ret_val = hw->nvm.ops.read(hw,
978 		ret_val = hw->nvm.ops.read(hw,
984 	if (ret_val) {
986 		return ret_val;
1012 	s32 ret_val;
1026 		ret_val = e1000_set_default_fc_generic(hw);
1027 		if (ret_val)
1028 			return ret_val;
1040 	ret_val = hw->mac.ops.setup_physical_interface(hw);
1041 	if (ret_val)
1042 		return ret_val;
1139 	s32 ret_val;
1163 		ret_val = mac->ops.check_for_link(hw);
1164 		if (ret_val) {
1166 			return ret_val;
1187 	s32 ret_val;
1198 	ret_val = e1000_commit_fc_settings_generic(hw);
1199 	if (ret_val)
1200 		return ret_val;
1220 		ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1225 	return ret_val;
1362 	s32 ret_val = E1000_SUCCESS;
1376 			ret_val = e1000_force_mac_fc_generic(hw);
1379 			ret_val = e1000_force_mac_fc_generic(hw);
1382 	if (ret_val) {
1384 		return ret_val;
1397 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1398 		if (ret_val)
1399 			return ret_val;
1400 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1401 		if (ret_val)
1402 			return ret_val;
1406 			return ret_val;
1415 		ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1417 		if (ret_val)
1418 			return ret_val;
1419 		ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1421 		if (ret_val)
1422 			return ret_val;
1512 		ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1513 		if (ret_val) {
1515 			return ret_val;
1524 		ret_val = e1000_force_mac_fc_generic(hw);
1525 		if (ret_val) {
1527 			return ret_val;
1545 			return ret_val;
1648 		ret_val = e1000_force_mac_fc_generic(hw);
1649 		if (ret_val) {
1651 			return ret_val;
1754 	s32 ret_val;
1758 	ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1759 	if (ret_val) {
1761 		return ret_val;
1778 	s32 ret_val;
1787 	ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1788 	if (ret_val)
1789 		return ret_val;
2306 	s32 ret_val = E1000_SUCCESS;
2313 			ret_val = -E1000_ERR_SWFW_SYNC;
2332 		ret_val = -E1000_ERR_SWFW_SYNC;
2342 	return ret_val;