dev/e1000/e1000_ich8lan.c

642 	struct e1000_nvm_info *nvm = &hw->nvm;
650 	nvm->type = e1000_nvm_flash_sw;
659 		nvm->flash_base_addr = 0;
663 		nvm->flash_bank_size = nvm_size / 2;
665 		nvm->flash_bank_size /= sizeof(u16);
685 		nvm->flash_base_addr = sector_base_addr
691 		nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
693 		nvm->flash_bank_size /= 2;
695 		nvm->flash_bank_size /= sizeof(u16);
698 	nvm->word_size = E1000_SHADOW_RAM_WORDS;
701 	for (i = 0; i < nvm->word_size; i++) {
707 	nvm->ops.acquire	= e1000_acquire_nvm_ich8lan;
708 	nvm->ops.release	= e1000_release_nvm_ich8lan;
710 		nvm->ops.read	= e1000_read_nvm_spt;
711 		nvm->ops.update	= e1000_update_nvm_checksum_spt;
713 		nvm->ops.read	= e1000_read_nvm_ich8lan;
714 		nvm->ops.update	= e1000_update_nvm_checksum_ich8lan;
716 	nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
717 	nvm->ops.validate	= e1000_validate_nvm_checksum_ich8lan;
718 	nvm->ops.write		= e1000_write_nvm_ich8lan;
1839 	hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
2369 		ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2374 		ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
3423 	struct e1000_nvm_info *nvm = &hw->nvm;
3424 	u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3438 		bank1_offset = nvm->flash_bank_size;
3529 	struct e1000_nvm_info *nvm = &hw->nvm;
3540 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3542 		DEBUGOUT("nvm parameter(s) out of bounds\n");
3547 	nvm->ops.acquire(hw);
3555 	act_offset = (bank) ? nvm->flash_bank_size : 0;
3603 	nvm->ops.release(hw);
3624 	struct e1000_nvm_info *nvm = &hw->nvm;
3633 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3635 		DEBUGOUT("nvm parameter(s) out of bounds\n");
3640 	nvm->ops.acquire(hw);
3648 	act_offset = (bank) ? nvm->flash_bank_size : 0;
3665 	nvm->ops.release(hw);
3902 			     hw->nvm.flash_base_addr);
3977 			     hw->nvm.flash_base_addr);
4044 	struct e1000_nvm_info *nvm = &hw->nvm;
4050 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
4052 		DEBUGOUT("nvm parameter(s) out of bounds\n");
4056 	nvm->ops.acquire(hw);
4063 	nvm->ops.release(hw);
4081 	struct e1000_nvm_info *nvm = &hw->nvm;
4093 	if (nvm->type != e1000_nvm_flash_sw)
4096 	nvm->ops.acquire(hw);
4109 		new_bank_offset = nvm->flash_bank_size;
4115 		old_bank_offset = nvm->flash_bank_size;
4213 	nvm->ops.release(hw);
4219 		nvm->ops.reload(hw);
4243 	struct e1000_nvm_info *nvm = &hw->nvm;
4255 	if (nvm->type != e1000_nvm_flash_sw)
4258 	nvm->ops.acquire(hw);
4271 		new_bank_offset = nvm->flash_bank_size;
4277 		old_bank_offset = nvm->flash_bank_size;
4366 	nvm->ops.release(hw);
4372 		nvm->ops.reload(hw);
4421 	ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4427 		ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4430 		ret_val = hw->nvm.ops.update(hw);
4468 			     hw->nvm.flash_base_addr);
4560 			     hw->nvm.flash_base_addr);
4724 	struct e1000_nvm_info *nvm = &hw->nvm;
4729 	u32 flash_bank_size = nvm->flash_bank_size * 2;
4773 	flash_linear_addr = hw->nvm.flash_base_addr;
4849 	ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4885 	ret_val = hw->nvm.ops.valid_led_default(hw, &data);