Lines Matching defs:ret_val
205 s32 ret_val = 0;
210 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
211 if (ret_val || (phy_reg == 0xFFFF))
215 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
216 if (ret_val || (phy_reg == 0xFFFF)) {
238 ret_val = e1000_set_mdio_slow_mode_hv(hw);
239 if (!ret_val)
240 ret_val = e1000_get_phy_id(hw);
244 if (ret_val)
320 s32 ret_val;
335 ret_val = hw->phy.ops.acquire(hw);
336 if (ret_val) {
381 ret_val = -E1000_ERR_PHY;
401 ret_val = -E1000_ERR_PHY;
409 if (!ret_val) {
422 ret_val = e1000_phy_hw_reset_generic(hw);
423 if (ret_val)
432 ret_val = hw->phy.ops.check_reset_block(hw);
433 if (ret_val)
445 return ret_val;
457 s32 ret_val;
484 ret_val = e1000_init_phy_workarounds_pchlan(hw);
485 if (ret_val)
486 return ret_val;
491 ret_val = e1000_get_phy_id(hw);
492 if (ret_val)
493 return ret_val;
507 ret_val = e1000_set_mdio_slow_mode_hv(hw);
508 if (ret_val)
509 return ret_val;
510 ret_val = e1000_get_phy_id(hw);
511 if (ret_val)
512 return ret_val;
535 ret_val = -E1000_ERR_PHY;
539 return ret_val;
551 s32 ret_val;
575 ret_val = e1000_determine_phy_address(hw);
576 if (ret_val) {
579 ret_val = e1000_determine_phy_address(hw);
580 if (ret_val) {
582 return ret_val;
590 ret_val = e1000_get_phy_id(hw);
591 if (ret_val)
592 return ret_val;
853 s32 ret_val;
857 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
858 if (ret_val)
859 return ret_val;
862 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
865 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
868 return ret_val;
918 s32 ret_val;
938 ret_val = hw->phy.ops.acquire(hw);
939 if (ret_val)
940 return ret_val;
942 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
943 if (ret_val)
952 ret_val = e1000_read_emi_reg_locked(hw, lpa,
954 if (ret_val)
958 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
959 if (ret_val)
983 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
985 if (ret_val)
989 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
994 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
995 if (ret_val)
998 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
1002 return ret_val;
1020 s32 ret_val = E1000_SUCCESS;
1024 ret_val = hw->phy.ops.acquire(hw);
1025 if (ret_val)
1026 return ret_val;
1028 ret_val =
1031 if (ret_val)
1034 ret_val =
1039 if (ret_val)
1047 ret_val =
1062 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
1063 if (ret_val)
1064 return ret_val;
1084 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1085 if (ret_val)
1086 return ret_val;
1092 return ret_val;
1270 s32 ret_val = E1000_SUCCESS;
1316 ret_val = hw->phy.ops.acquire(hw);
1317 if (ret_val)
1321 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1322 if (ret_val)
1336 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1338 if (ret_val)
1344 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1347 if (ret_val)
1354 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1355 if (ret_val)
1385 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1387 if (ret_val)
1394 if (ret_val)
1395 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1399 return ret_val;
1419 s32 ret_val = E1000_SUCCESS;
1448 ret_val = -E1000_ERR_PHY;
1470 ret_val = hw->phy.ops.acquire(hw);
1471 if (ret_val)
1479 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1480 if (ret_val) {
1490 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1492 if (ret_val)
1506 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1507 if (ret_val)
1513 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1514 if (ret_val)
1542 if (ret_val)
1543 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1547 return ret_val;
1561 s32 ret_val, tipg_reg = 0;
1580 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1581 if (ret_val)
1582 return ret_val;
1585 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1586 if (ret_val)
1587 return ret_val;
1617 ret_val = hw->phy.ops.acquire(hw);
1618 if (ret_val)
1619 return ret_val;
1625 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1652 if (ret_val)
1653 return ret_val;
1660 ret_val = hw->phy.ops.acquire(hw);
1661 if (ret_val)
1662 return ret_val;
1664 ret_val = hw->phy.ops.read_reg_locked(hw,
1667 if (ret_val) {
1669 return ret_val;
1676 ret_val =
1681 if (ret_val)
1682 return ret_val;
1684 ret_val = hw->phy.ops.acquire(hw);
1685 if (ret_val)
1686 return ret_val;
1688 ret_val = hw->phy.ops.write_reg_locked(hw,
1692 if (ret_val)
1693 return ret_val;
1718 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1719 if (ret_val)
1720 return ret_val;
1727 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1728 if (ret_val)
1729 return ret_val;
1763 ret_val = e1000_k1_workaround_lv(hw);
1764 if (ret_val)
1765 return ret_val;
1769 ret_val = e1000_link_stall_workaround_hv(hw);
1770 if (ret_val)
1771 return ret_val;
1799 ret_val = e1000_set_eee_pchlan(hw);
1800 if (ret_val)
1801 return ret_val;
1821 ret_val = e1000_config_fc_after_link_up_generic(hw);
1822 if (ret_val)
1825 return ret_val;
1899 s32 ret_val = E1000_SUCCESS;
1916 ret_val = -E1000_ERR_CONFIG;
1939 ret_val = -E1000_ERR_CONFIG;
1944 return ret_val;
2053 s32 ret_val;
2055 ret_val = e1000_acquire_swflag_ich8lan(hw);
2056 if (ret_val)
2131 s32 ret_val;
2133 ret_val = e1000_acquire_swflag_ich8lan(hw);
2135 if (ret_val)
2174 s32 ret_val;
2180 ret_val = hw->phy.ops.acquire(hw);
2181 if (ret_val)
2184 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2185 if (ret_val)
2244 s32 ret_val;
2248 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2249 if (ret_val)
2250 return ret_val;
2283 s32 ret_val = E1000_SUCCESS;
2297 return ret_val;
2316 return ret_val;
2319 ret_val = hw->phy.ops.acquire(hw);
2320 if (ret_val)
2321 return ret_val;
2352 ret_val = e1000_write_smbus_addr(hw);
2353 if (ret_val)
2357 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2359 if (ret_val)
2369 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2371 if (ret_val)
2374 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2376 if (ret_val)
2388 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2390 if (ret_val)
2396 return ret_val;
2411 s32 ret_val = E1000_SUCCESS;
2421 ret_val = hw->phy.ops.acquire(hw);
2422 if (ret_val)
2423 return ret_val;
2428 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2430 if (ret_val)
2444 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2446 if (ret_val)
2460 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2462 if (ret_val)
2467 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2469 if (ret_val)
2473 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2478 return ret_val;
2493 s32 ret_val;
2501 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2503 if (ret_val)
2504 return ret_val;
2511 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2513 if (ret_val)
2514 return ret_val;
2546 s32 ret_val = 0;
2553 return ret_val;
2555 ret_val = hw->phy.ops.acquire(hw);
2556 if (ret_val)
2557 return ret_val;
2571 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2572 if (ret_val)
2598 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2603 return ret_val;
2613 s32 ret_val;
2618 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2619 if (ret_val)
2620 return ret_val;
2624 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2626 return ret_val;
2636 s32 ret_val = E1000_SUCCESS;
2646 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2647 if (ret_val)
2648 return ret_val;
2655 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2656 if (ret_val)
2657 return ret_val;
2660 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2662 if (ret_val)
2663 return ret_val;
2672 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2674 if (ret_val)
2675 return ret_val;
2680 ret_val = hw->phy.ops.acquire(hw);
2681 if (ret_val)
2682 return ret_val;
2685 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2687 if (ret_val)
2688 return ret_val;
2693 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2694 if (ret_val)
2695 return ret_val;
2698 ret_val = hw->phy.ops.acquire(hw);
2699 if (ret_val)
2700 return ret_val;
2701 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2702 if (ret_val)
2704 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2706 if (ret_val)
2710 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2714 return ret_val;
2725 s32 ret_val;
2729 ret_val = hw->phy.ops.acquire(hw);
2730 if (ret_val)
2732 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2733 if (ret_val)
2784 s32 ret_val = E1000_SUCCESS;
2796 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2798 if (ret_val)
2799 return ret_val;
2837 ret_val = e1000_read_kmrn_reg_generic(hw,
2840 if (ret_val)
2841 return ret_val;
2842 ret_val = e1000_write_kmrn_reg_generic(hw,
2845 if (ret_val)
2846 return ret_val;
2847 ret_val = e1000_read_kmrn_reg_generic(hw,
2850 if (ret_val)
2851 return ret_val;
2854 ret_val = e1000_write_kmrn_reg_generic(hw,
2857 if (ret_val)
2858 return ret_val;
2864 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2865 if (ret_val)
2866 return ret_val;
2869 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2870 if (ret_val)
2871 return ret_val;
2875 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2876 if (ret_val)
2877 return ret_val;
2878 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2879 if (ret_val)
2880 return ret_val;
2882 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2884 if (ret_val)
2885 return ret_val;
2896 ret_val = e1000_read_kmrn_reg_generic(hw,
2899 if (ret_val)
2900 return ret_val;
2901 ret_val = e1000_write_kmrn_reg_generic(hw,
2904 if (ret_val)
2905 return ret_val;
2906 ret_val = e1000_read_kmrn_reg_generic(hw,
2909 if (ret_val)
2910 return ret_val;
2913 ret_val = e1000_write_kmrn_reg_generic(hw,
2916 if (ret_val)
2917 return ret_val;
2922 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2923 if (ret_val)
2924 return ret_val;
2927 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2928 if (ret_val)
2929 return ret_val;
2933 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2934 if (ret_val)
2935 return ret_val;
2936 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2937 if (ret_val)
2938 return ret_val;
2940 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2942 if (ret_val)
2943 return ret_val;
2958 s32 ret_val = E1000_SUCCESS;
2966 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2967 if (ret_val)
2968 return ret_val;
2970 ret_val = hw->phy.ops.acquire(hw);
2971 if (ret_val)
2972 return ret_val;
2974 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2975 if (ret_val)
2978 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2982 return ret_val;
2994 s32 ret_val = E1000_SUCCESS;
3003 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
3004 if (ret_val)
3005 return ret_val;
3014 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
3016 if (ret_val)
3017 return ret_val;
3019 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
3021 if (ret_val)
3022 return ret_val;
3032 return ret_val;
3101 s32 ret_val = E1000_SUCCESS;
3115 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
3116 if (ret_val)
3117 return ret_val;
3120 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
3121 if (ret_val)
3122 return ret_val;
3136 ret_val = e1000_sw_lcd_config_ich8lan(hw);
3137 if (ret_val)
3138 return ret_val;
3141 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
3152 ret_val = hw->phy.ops.acquire(hw);
3153 if (ret_val)
3154 return ret_val;
3155 ret_val = e1000_write_emi_reg_locked(hw,
3161 return ret_val;
3174 s32 ret_val = E1000_SUCCESS;
3183 ret_val = e1000_phy_hw_reset_generic(hw);
3184 if (ret_val)
3185 return ret_val;
3203 s32 ret_val;
3207 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3208 if (ret_val)
3209 return ret_val;
3239 s32 ret_val = E1000_SUCCESS;
3263 ret_val = phy->ops.read_reg(hw,
3266 if (ret_val)
3267 return ret_val;
3269 ret_val = phy->ops.write_reg(hw,
3272 if (ret_val)
3273 return ret_val;
3287 ret_val = phy->ops.read_reg(hw,
3290 if (ret_val)
3291 return ret_val;
3294 ret_val = phy->ops.write_reg(hw,
3297 if (ret_val)
3298 return ret_val;
3300 ret_val = phy->ops.read_reg(hw,
3303 if (ret_val)
3304 return ret_val;
3307 ret_val = phy->ops.write_reg(hw,
3310 if (ret_val)
3311 return ret_val;
3335 s32 ret_val = E1000_SUCCESS;
3355 ret_val = phy->ops.read_reg(hw,
3358 if (ret_val)
3359 return ret_val;
3362 ret_val = phy->ops.write_reg(hw,
3365 if (ret_val)
3366 return ret_val;
3368 ret_val = phy->ops.read_reg(hw,
3371 if (ret_val)
3372 return ret_val;
3375 ret_val = phy->ops.write_reg(hw,
3378 if (ret_val)
3379 return ret_val;
3397 ret_val = phy->ops.read_reg(hw,
3400 if (ret_val)
3401 return ret_val;
3404 ret_val = phy->ops.write_reg(hw,
3409 return ret_val;
3428 s32 ret_val;
3445 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3447 if (ret_val)
3448 return ret_val;
3457 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3460 if (ret_val)
3461 return ret_val;
3490 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3492 if (ret_val)
3493 return ret_val;
3501 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3504 if (ret_val)
3505 return ret_val;
3532 s32 ret_val = E1000_SUCCESS;
3543 ret_val = -E1000_ERR_NVM;
3549 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3550 if (ret_val != E1000_SUCCESS) {
3558 ret_val = E1000_SUCCESS;
3568 ret_val =
3572 if (ret_val)
3583 ret_val =
3587 if (ret_val)
3606 if (ret_val)
3607 DEBUGOUT1("NVM read error: %d\n", ret_val);
3609 return ret_val;
3627 s32 ret_val = E1000_SUCCESS;
3636 ret_val = -E1000_ERR_NVM;
3642 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3643 if (ret_val != E1000_SUCCESS) {
3651 ret_val = E1000_SUCCESS;
3656 ret_val = e1000_read_flash_word_ich8lan(hw,
3659 if (ret_val)
3668 if (ret_val)
3669 DEBUGOUT1("NVM read error: %d\n", ret_val);
3671 return ret_val;
3684 s32 ret_val = -E1000_ERR_NVM;
3725 ret_val = E1000_SUCCESS;
3736 ret_val = E1000_SUCCESS;
3741 if (ret_val == E1000_SUCCESS) {
3757 return ret_val;
3859 s32 ret_val;
3868 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3870 if (ret_val)
3871 return ret_val;
3894 s32 ret_val = -E1000_ERR_NVM;
3907 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3908 if (ret_val != E1000_SUCCESS)
3918 ret_val = e1000_flash_cycle_ich8lan(hw,
3926 if (ret_val == E1000_SUCCESS) {
3951 return ret_val;
3968 s32 ret_val = -E1000_ERR_NVM;
3982 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3983 if (ret_val != E1000_SUCCESS)
4000 ret_val = e1000_flash_cycle_ich8lan(hw,
4008 if (ret_val == E1000_SUCCESS) {
4029 return ret_val;
4084 s32 ret_val;
4089 ret_val = e1000_update_nvm_checksum_generic(hw);
4090 if (ret_val)
4102 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4103 if (ret_val != E1000_SUCCESS) {
4111 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4112 if (ret_val)
4117 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4118 if (ret_val)
4126 ret_val = e1000_read_flash_dword_ich8lan(hw,
4139 if (ret_val)
4159 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4161 if (ret_val)
4168 if (ret_val) {
4182 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4184 if (ret_val)
4188 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4190 if (ret_val)
4195 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4197 if (ret_val)
4201 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4203 if (ret_val)
4218 if (!ret_val) {
4224 if (ret_val)
4225 DEBUGOUT1("NVM update error: %d\n", ret_val);
4227 return ret_val;
4246 s32 ret_val;
4251 ret_val = e1000_update_nvm_checksum_generic(hw);
4252 if (ret_val)
4264 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4265 if (ret_val != E1000_SUCCESS) {
4273 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4274 if (ret_val)
4279 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4280 if (ret_val)
4287 ret_val = e1000_read_flash_word_ich8lan(hw, i +
4290 if (ret_val)
4309 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4312 if (ret_val)
4316 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4319 if (ret_val)
4326 if (ret_val) {
4337 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4338 if (ret_val)
4342 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
4344 if (ret_val)
4354 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4356 if (ret_val)
4371 if (!ret_val) {
4377 if (ret_val)
4378 DEBUGOUT1("NVM update error: %d\n", ret_val);
4380 return ret_val;
4393 s32 ret_val;
4421 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4422 if (ret_val)
4423 return ret_val;
4427 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4428 if (ret_val)
4429 return ret_val;
4430 ret_val = hw->nvm.ops.update(hw);
4431 if (ret_val)
4432 return ret_val;
4454 s32 ret_val;
4473 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4474 if (ret_val != E1000_SUCCESS)
4512 ret_val =
4515 if (ret_val == E1000_SUCCESS)
4533 return ret_val;
4550 s32 ret_val;
4564 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4565 if (ret_val != E1000_SUCCESS)
4600 ret_val = e1000_flash_cycle_ich8lan(hw,
4603 if (ret_val == E1000_SUCCESS)
4622 return ret_val;
4655 s32 ret_val;
4663 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4665 if (!ret_val)
4666 return ret_val;
4670 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4671 if (ret_val == E1000_SUCCESS)
4692 s32 ret_val;
4697 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4698 if (!ret_val)
4699 return ret_val;
4704 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4705 if (ret_val == E1000_SUCCESS)
4730 s32 ret_val;
4781 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4782 if (ret_val)
4783 return ret_val;
4813 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4814 if (ret_val == E1000_SUCCESS)
4827 return ret_val;
4845 s32 ret_val;
4849 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4850 if (ret_val) {
4852 return ret_val;
4877 s32 ret_val;
4885 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4886 if (ret_val)
4887 return ret_val;
4945 s32 ret_val;
4949 ret_val = e1000_get_bus_info_pcie_generic(hw);
4959 return ret_val;
4974 s32 ret_val;
4982 ret_val = e1000_disable_pcie_master_generic(hw);
4983 if (ret_val)
5009 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
5010 if (ret_val)
5011 return ret_val;
5035 ret_val = e1000_acquire_swflag_ich8lan(hw);
5068 ret_val = hw->phy.ops.get_cfg_done(hw);
5069 if (ret_val)
5070 return ret_val;
5072 ret_val = e1000_post_phy_reset_ich8lan(hw);
5073 if (ret_val)
5074 return ret_val;
5110 s32 ret_val;
5118 ret_val = mac->ops.id_led_init(hw);
5120 if (ret_val)
5139 ret_val = e1000_phy_hw_reset_ich8lan(hw);
5140 if (ret_val)
5141 return ret_val;
5145 ret_val = mac->ops.setup_link(hw);
5181 return ret_val;
5277 s32 ret_val;
5298 ret_val = hw->mac.ops.setup_physical_interface(hw);
5299 if (ret_val)
5300 return ret_val;
5310 ret_val = hw->phy.ops.write_reg(hw,
5313 if (ret_val)
5314 return ret_val;
5331 s32 ret_val;
5345 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
5347 if (ret_val)
5348 return ret_val;
5349 ret_val = e1000_read_kmrn_reg_generic(hw,
5352 if (ret_val)
5353 return ret_val;
5355 ret_val = e1000_write_kmrn_reg_generic(hw,
5358 if (ret_val)
5359 return ret_val;
5363 ret_val = e1000_copper_link_setup_igp(hw);
5364 if (ret_val)
5365 return ret_val;
5369 ret_val = e1000_copper_link_setup_m88(hw);
5370 if (ret_val)
5371 return ret_val;
5375 ret_val = e1000_copper_link_setup_82577(hw);
5376 if (ret_val)
5377 return ret_val;
5380 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
5382 if (ret_val)
5383 return ret_val;
5399 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
5401 if (ret_val)
5402 return ret_val;
5422 s32 ret_val;
5431 ret_val = e1000_copper_link_setup_82577(hw);
5432 if (ret_val)
5433 return ret_val;
5451 s32 ret_val;
5455 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
5456 if (ret_val)
5457 return ret_val;
5462 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5465 return ret_val;
5487 s32 ret_val;
5500 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
5506 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5507 if (ret_val)
5508 return ret_val;
5510 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5511 if (ret_val)
5512 return ret_val;
5628 s32 ret_val;
5637 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5639 if (ret_val)
5642 ret_val = e1000_write_kmrn_reg_generic(hw,
5645 if (ret_val)
5670 s32 ret_val;
5691 ret_val = hw->phy.ops.acquire(hw);
5692 if (ret_val)
5698 ret_val =
5702 if (ret_val)
5780 ret_val = hw->phy.ops.acquire(hw);
5781 if (ret_val)
5802 s32 ret_val;
5808 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5809 if (ret_val) {
5810 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5811 return ret_val;
5822 ret_val = hw->phy.ops.acquire(hw);
5823 if (ret_val) {
5825 return ret_val;
5838 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5840 if (ret_val)
5849 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5851 if (ret_val)
5856 if (ret_val)
5857 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5859 return ret_val;
6024 s32 ret_val = E1000_SUCCESS;
6036 ret_val = e1000_get_auto_rd_done_generic(hw);
6037 if (ret_val) {
6043 ret_val = E1000_SUCCESS;
6064 ret_val = -E1000_ERR_CONFIG;
6068 return ret_val;
6098 s32 ret_val;
6123 ret_val = hw->phy.ops.acquire(hw);
6124 if (ret_val)
6126 ret_val = hw->phy.ops.set_page(hw,
6128 if (ret_val)
6166 s32 ret_val;
6174 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6176 if (ret_val)
6177 return ret_val;
6183 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6185 if (ret_val)
6186 return ret_val;