Lines Matching refs:phy
161 struct e1000_phy_info *phy = &hw->phy;
167 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
168 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
170 if (hw->phy.media_type != e1000_media_type_copper) {
171 phy->type = e1000_phy_none;
175 phy->ops.power_up = e1000_power_up_phy_copper;
176 phy->ops.power_down = e1000_power_down_phy_copper_base;
178 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
179 phy->reset_delay_us = 100;
181 phy->ops.acquire = e1000_acquire_phy_base;
182 phy->ops.check_reset_block = e1000_check_reset_block_generic;
183 phy->ops.commit = e1000_phy_sw_reset_generic;
184 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
185 phy->ops.release = e1000_release_phy_base;
190 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
193 phy->ops.reset = e1000_phy_hw_reset_generic;
201 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
202 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
208 phy->ops.read_reg = e1000_read_phy_reg_82580;
209 phy->ops.write_reg = e1000_write_phy_reg_82580;
213 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
214 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
217 phy->ops.read_reg = e1000_read_phy_reg_igp;
218 phy->ops.write_reg = e1000_write_phy_reg_igp;
222 /* Set phy->phy_addr and phy->id. */
225 /* Verify phy id and set remaining function pointers */
226 switch (phy->id) {
232 phy->type = e1000_phy_m88;
233 phy->ops.check_polarity = e1000_check_polarity_m88;
234 phy->ops.get_info = e1000_get_phy_info_m88;
235 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
236 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
239 phy->type = e1000_phy_m88;
240 phy->ops.check_polarity = e1000_check_polarity_m88;
241 phy->ops.get_info = e1000_get_phy_info_m88;
242 phy->ops.get_cable_length = e1000_get_cable_length_m88;
243 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
247 phy->type = e1000_phy_igp_3;
248 phy->ops.check_polarity = e1000_check_polarity_igp;
249 phy->ops.get_info = e1000_get_phy_info_igp;
250 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
251 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
252 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
253 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
257 phy->type = e1000_phy_82580;
258 phy->ops.check_polarity = e1000_check_polarity_82577;
259 phy->ops.get_info = e1000_get_phy_info_82577;
260 phy->ops.get_cable_length = e1000_get_cable_length_82577;
261 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
262 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
263 phy->ops.force_speed_duplex =
267 phy->type = e1000_phy_i210;
268 phy->ops.check_polarity = e1000_check_polarity_m88;
269 phy->ops.get_info = e1000_get_phy_info_m88;
270 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
271 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
272 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
273 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
281 switch (phy->id) {
286 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 2);
289 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_MAC_CTRL_1,
383 (hw->phy.media_type == e1000_media_type_copper)
431 /* set lan id for port to determine which phy lock to use */
532 hw->phy.ops.init_params = e1000_init_phy_params_82575;
557 ret_val = hw->phy.ops.acquire(hw);
563 hw->phy.ops.release(hw);
590 ret_val = hw->phy.ops.acquire(hw);
596 hw->phy.ops.release(hw);
611 struct e1000_phy_info *phy = &hw->phy;
619 /* some i354 devices need an extra read for phy id */
627 * work. The result of this function should mean phy->phy_addr
628 * and phy->id are set correctly.
631 phy->addr = 1;
642 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
651 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
662 /* Power on sgmii phy if it is disabled */
673 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
677 phy_id, phy->addr);
686 phy->addr);
691 if (phy->addr == 8) {
692 phy->addr = 0;
714 struct e1000_phy_info *phy = &hw->phy;
725 if (!(hw->phy.ops.write_reg))
732 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
736 ret_val = hw->phy.ops.commit(hw);
740 if (phy->id == M88E1512_E_PHY_ID)
761 struct e1000_phy_info *phy = &hw->phy;
767 if (!(hw->phy.ops.read_reg))
770 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
776 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
782 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
785 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
791 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
799 if (phy->smart_speed == e1000_smart_speed_on) {
800 ret_val = phy->ops.read_reg(hw,
807 ret_val = phy->ops.write_reg(hw,
812 } else if (phy->smart_speed == e1000_smart_speed_off) {
813 ret_val = phy->ops.read_reg(hw,
820 ret_val = phy->ops.write_reg(hw,
847 struct e1000_phy_info *phy = &hw->phy;
868 if (phy->smart_speed == e1000_smart_speed_on)
870 else if (phy->smart_speed == e1000_smart_speed_off)
894 struct e1000_phy_info *phy = &hw->phy;
909 if (phy->smart_speed == e1000_smart_speed_on)
911 else if (phy->smart_speed == e1000_smart_speed_off)
913 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
914 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
915 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1027 (hw->phy.type == e1000_phy_igp_3))
1050 if (hw->phy.media_type != e1000_media_type_copper)
1074 if (hw->phy.media_type != e1000_media_type_copper) {
1108 struct e1000_phy_info *phy = &hw->phy;
1116 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1120 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1128 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1132 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1147 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1154 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1172 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1270 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1435 /* allow time for SFP cage time to power up phy */
1438 ret_val = hw->phy.ops.reset(hw);
1444 switch (hw->phy.type) {
1448 switch (hw->phy.id) {
1504 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1535 /* sgmii mode lets the phy handle forcing speed/duplex */
1645 /* Set internal phy as default */
1657 hw->phy.media_type = e1000_media_type_internal_serdes;
1660 hw->phy.media_type = e1000_media_type_copper;
1663 /* Get phy control interface type set (MDIO vs. I2C)*/
1665 hw->phy.media_type = e1000_media_type_copper;
1675 (hw->phy.media_type == e1000_media_type_unknown)) {
1680 hw->phy.media_type = e1000_media_type_internal_serdes;
1683 hw->phy.media_type = e1000_media_type_copper;
1697 if (hw->phy.media_type == e1000_media_type_copper)
1757 hw->phy.media_type = e1000_media_type_internal_serdes;
1760 hw->phy.media_type = e1000_media_type_internal_serdes;
1763 hw->phy.media_type = e1000_media_type_copper;
1765 hw->phy.media_type = e1000_media_type_unknown;
1770 hw->phy.media_type = e1000_media_type_unknown;
1800 switch (hw->phy.media_type) {
1973 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2139 ret_val = hw->phy.ops.acquire(hw);
2145 hw->phy.ops.release(hw);
2165 ret_val = hw->phy.ops.acquire(hw);
2171 hw->phy.ops.release(hw);
2559 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2564 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2566 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2592 struct e1000_phy_info *phy = &hw->phy;
2598 if (phy->id != M88E1512_E_PHY_ID)
2602 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2606 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2610 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2614 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2618 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2622 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2626 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2630 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2634 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2639 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2643 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2648 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2653 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2658 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2662 ret_val = phy->ops.commit(hw);
2681 struct e1000_phy_info *phy = &hw->phy;
2687 if (phy->id != M88E1543_E_PHY_ID)
2691 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2695 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2699 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2703 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2707 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2711 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2715 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2719 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2723 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2728 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2732 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D);
2737 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2742 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2747 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2752 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2757 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2761 ret_val = phy->ops.commit(hw);
2788 (hw->phy.media_type != e1000_media_type_copper))
2838 struct e1000_phy_info *phy = &hw->phy;
2844 if ((hw->phy.media_type != e1000_media_type_copper) ||
2845 ((phy->id != M88E1543_E_PHY_ID) &&
2846 (phy->id != M88E1512_E_PHY_ID)))
2851 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2855 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2861 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2867 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2920 struct e1000_phy_info *phy = &hw->phy;
2927 if ((hw->phy.media_type != e1000_media_type_copper) ||
2928 ((phy->id != M88E1543_E_PHY_ID) &&
2929 (phy->id != M88E1512_E_PHY_ID)))