dev/e1000/e1000_82575.c

443 	struct e1000_nvm_info *nvm = &hw->nvm;
462 	nvm->word_size = 1 << size;
464 		nvm->opcode_bits = 8;
465 		nvm->delay_usec = 1;
467 		switch (nvm->override) {
469 			nvm->page_size = 32;
470 			nvm->address_bits = 16;
473 			nvm->page_size = 8;
474 			nvm->address_bits = 8;
477 			nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
478 			nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
482 		if (nvm->word_size == (1 << 15))
483 			nvm->page_size = 128;
485 		nvm->type = e1000_nvm_eeprom_spi;
487 		nvm->type = e1000_nvm_flash_hw;
491 	nvm->ops.acquire = e1000_acquire_nvm_82575;
492 	nvm->ops.release = e1000_release_nvm_82575;
493 	if (nvm->word_size < (1 << 15))
494 		nvm->ops.read = e1000_read_nvm_eerd;
496 		nvm->ops.read = e1000_read_nvm_spi;
498 	nvm->ops.write = e1000_write_nvm_spi;
499 	nvm->ops.validate = e1000_validate_nvm_checksum_generic;
500 	nvm->ops.update = e1000_update_nvm_checksum_generic;
501 	nvm->ops.valid_led_default = e1000_valid_led_default_82575;
506 		nvm->ops.validate = e1000_validate_nvm_checksum_82580;
507 		nvm->ops.update = e1000_update_nvm_checksum_82580;
510 		nvm->ops.validate = e1000_validate_nvm_checksum_i350;
511 		nvm->ops.update = e1000_update_nvm_checksum_i350;
531 	hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
1547 			ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1793 	ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
2198 	ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2351 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2388 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2396 	ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2422 	ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2462 	ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2471 		ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,