dev/e1000/e1000_82575.c

162 	s32 ret_val = E1000_SUCCESS;
223 	ret_val = e1000_get_phy_id_82575(hw);
276 		ret_val = -E1000_ERR_PHY;
286 		ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 2);
287 		if (ret_val)
289 		ret_val = phy->ops.read_reg(hw, E1000_M88E1112_MAC_CTRL_1,
291 		if (ret_val)
304 		ret_val = e1000_initialize_M88E1512_phy(hw);
309 		ret_val = e1000_initialize_M88E1543_phy(hw);
317 	return ret_val;
548 	s32 ret_val = -E1000_ERR_PARAM;
557 	ret_val = hw->phy.ops.acquire(hw);
558 	if (ret_val)
561 	ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
566 	return ret_val;
581 	s32 ret_val = -E1000_ERR_PARAM;
590 	ret_val = hw->phy.ops.acquire(hw);
591 	if (ret_val)
594 	ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
599 	return ret_val;
612 	s32  ret_val = E1000_SUCCESS;
632 		ret_val = e1000_get_phy_id(hw);
654 			ret_val = -E1000_ERR_PHY;
658 		ret_val = e1000_get_phy_id(hw);
674 		ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
675 		if (ret_val == E1000_SUCCESS) {
693 		ret_val = -E1000_ERR_PHY;
695 		ret_val = e1000_get_phy_id(hw);
702 	return ret_val;
713 	s32 ret_val = E1000_SUCCESS;
732 	ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
733 	if (ret_val)
736 	ret_val = hw->phy.ops.commit(hw);
737 	if (ret_val)
741 		ret_val = e1000_initialize_M88E1512_phy(hw);
743 	return ret_val;
762 	s32 ret_val = E1000_SUCCESS;
770 	ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
771 	if (ret_val)
776 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
778 		if (ret_val)
782 		ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
785 		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
787 		if (ret_val)
791 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
800 			ret_val = phy->ops.read_reg(hw,
803 			if (ret_val)
807 			ret_val = phy->ops.write_reg(hw,
810 			if (ret_val)
813 			ret_val = phy->ops.read_reg(hw,
816 			if (ret_val)
820 			ret_val = phy->ops.write_reg(hw,
823 			if (ret_val)
829 	return ret_val;
936 	s32 ret_val = E1000_SUCCESS;
940 	ret_val = e1000_acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
941 	if (ret_val)
969 	ret_val = e1000_acquire_nvm_generic(hw);
970 	if (ret_val)
974 	return ret_val;
1046 	s32 ret_val;
1051 		ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1054 		ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1057 	return ret_val;
1069 	s32 ret_val;
1075 		ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1090 		ret_val = e1000_config_fc_after_link_up_generic(hw);
1091 		if (ret_val)
1094 		ret_val = e1000_check_for_copper_link_generic(hw);
1097 	return ret_val;
1109 	s32 ret_val;
1116 	ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1117 	if (ret_val)
1118 		return ret_val;
1120 	ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1121 	if (ret_val)
1122 		return ret_val;
1128 	ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1129 	if (ret_val)
1130 		return ret_val;
1132 	ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1133 	if (ret_val)
1134 		return ret_val;
1147 		ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1148 		if (ret_val)
1149 			return ret_val;
1154 		ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1155 		if (ret_val)
1156 			return ret_val;
1302 	s32 ret_val;
1310 	ret_val = e1000_disable_pcie_master_generic(hw);
1311 	if (ret_val)
1315 	ret_val = e1000_set_pcie_completion_timeout(hw);
1316 	if (ret_val)
1333 	ret_val = e1000_get_auto_rd_done_generic(hw);
1334 	if (ret_val) {
1352 	ret_val = e1000_check_alt_mac_addr_generic(hw);
1354 	return ret_val;
1366 	s32 ret_val;
1371 	ret_val = mac->ops.id_led_init(hw);
1372 	if (ret_val) {
1381 	ret_val = e1000_init_hw_base(hw);
1393 	return ret_val;
1407 	s32 ret_val;
1430 	ret_val = e1000_setup_serdes_link_82575(hw);
1431 	if (ret_val)
1438 		ret_val = hw->phy.ops.reset(hw);
1439 		if (ret_val) {
1460 			ret_val = e1000_copper_link_setup_m88_gen2(hw);
1463 			ret_val = e1000_copper_link_setup_m88(hw);
1468 		ret_val = e1000_copper_link_setup_igp(hw);
1471 		ret_val = e1000_copper_link_setup_82577(hw);
1474 		ret_val = -E1000_ERR_PHY;
1478 	if (ret_val)
1481 	ret_val = e1000_setup_copper_link_generic(hw);
1483 	return ret_val;
1499 	s32 ret_val = E1000_SUCCESS;
1506 		return ret_val;
1547 			ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1548 			if (ret_val) {
1550 				return ret_val;
1624 	return ret_val;
1641 	s32 ret_val = E1000_SUCCESS;
1673 		ret_val = e1000_set_sfp_media_type_82575(hw);
1674 		if ((ret_val != E1000_SUCCESS) ||
1707 	return ret_val;
1719 	s32 ret_val = E1000_ERR_CONFIG;
1735 		ret_val = e1000_read_sfp_data_byte(hw,
1738 		if (ret_val == E1000_SUCCESS)
1743 	if (ret_val != E1000_SUCCESS)
1746 	ret_val = e1000_read_sfp_data_byte(hw,
1749 	if (ret_val != E1000_SUCCESS)
1772 	ret_val = E1000_SUCCESS;
1776 	return ret_val;
1789 	s32 ret_val;
1793 	ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1794 	if (ret_val) {
1811 	return ret_val;
1872 	s32 ret_val;
1881 	ret_val = e1000_check_alt_mac_addr_generic(hw);
1882 	if (ret_val)
1885 	ret_val = e1000_read_mac_addr_generic(hw);
1888 	return ret_val;
1991 	s32 ret_val = E1000_SUCCESS;
2012 	ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2014 	if (ret_val)
2019 	ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2026 	return ret_val;
2135 	s32 ret_val;
2139 	ret_val = hw->phy.ops.acquire(hw);
2140 	if (ret_val)
2143 	ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2148 	return ret_val;
2161 	s32 ret_val;
2165 	ret_val = hw->phy.ops.acquire(hw);
2166 	if (ret_val)
2169 	ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2174 	return ret_val;
2187 	s32 ret_val = E1000_SUCCESS;
2198 	ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2201 	if (ret_val) {
2213 	return ret_val;
2225 	s32 ret_val = E1000_SUCCESS;
2246 	ret_val = e1000_disable_pcie_master_generic(hw);
2247 	if (ret_val)
2282 	ret_val = e1000_get_auto_rd_done_generic(hw);
2283 	if (ret_val) {
2299 	ret_val = e1000_reset_mdicnfg_82580(hw);
2300 	if (ret_val)
2304 	ret_val = e1000_check_alt_mac_addr_generic(hw);
2310 	return ret_val;
2325 	u16 ret_val = 0;
2328 		ret_val = e1000_82580_rxpbs_table[data];
2330 	return ret_val;
2344 	s32 ret_val = E1000_SUCCESS;
2351 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2352 		if (ret_val) {
2361 		ret_val = -E1000_ERR_NVM;
2366 	return ret_val;
2381 	s32 ret_val;
2388 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2389 		if (ret_val) {
2396 	ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2398 	if (ret_val)
2402 	return ret_val;
2415 	s32 ret_val;
2422 	ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2423 	if (ret_val) {
2436 		ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2438 		if (ret_val != E1000_SUCCESS)
2443 	return ret_val;
2456 	s32 ret_val;
2462 	ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2463 	if (ret_val) {
2471 		ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2473 		if (ret_val) {
2481 		ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2482 		if (ret_val)
2487 	return ret_val;
2500 	s32 ret_val = E1000_SUCCESS;
2508 		ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2510 		if (ret_val != E1000_SUCCESS)
2515 	return ret_val;
2528 	s32 ret_val = E1000_SUCCESS;
2536 		ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2537 		if (ret_val != E1000_SUCCESS)
2542 	return ret_val;
2555 	s32 ret_val;
2559 	ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2560 	if (ret_val)
2561 		return ret_val;
2564 		ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2566 		ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2568 	return ret_val;
2593 	s32 ret_val = E1000_SUCCESS;
2602 	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2603 	if (ret_val)
2606 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2607 	if (ret_val)
2610 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2611 	if (ret_val)
2614 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2615 	if (ret_val)
2618 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2619 	if (ret_val)
2622 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2623 	if (ret_val)
2626 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2627 	if (ret_val)
2630 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2631 	if (ret_val)
2634 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2635 	if (ret_val)
2639 	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2640 	if (ret_val)
2643 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2644 	if (ret_val)
2648 	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2649 	if (ret_val)
2653 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2654 	if (ret_val)
2658 	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2659 	if (ret_val)
2662 	ret_val = phy->ops.commit(hw);
2663 	if (ret_val) {
2665 		return ret_val;
2670 	return ret_val;
2682 	s32 ret_val = E1000_SUCCESS;
2691 	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2692 	if (ret_val)
2695 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2696 	if (ret_val)
2699 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2700 	if (ret_val)
2703 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2704 	if (ret_val)
2707 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2708 	if (ret_val)
2711 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2712 	if (ret_val)
2715 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2716 	if (ret_val)
2719 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2720 	if (ret_val)
2723 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2724 	if (ret_val)
2728 	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2729 	if (ret_val)
2732 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D);
2733 	if (ret_val)
2737 	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2738 	if (ret_val)
2742 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2743 	if (ret_val)
2747 	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2748 	if (ret_val)
2752 	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2753 	if (ret_val)
2757 	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2758 	if (ret_val)
2761 	ret_val = phy->ops.commit(hw);
2762 	if (ret_val) {
2764 		return ret_val;
2769 	return ret_val;
2839 	s32 ret_val = E1000_SUCCESS;
2851 		ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2852 		if (ret_val)
2855 		ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2857 		if (ret_val)
2861 		ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2863 		if (ret_val)
2867 		ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2868 		if (ret_val)
2872 		ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2875 		if (ret_val)
2888 		ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2893 		ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2896 		if (ret_val)
2901 		ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2907 	return ret_val;
2921 	s32 ret_val = E1000_SUCCESS;
2932 	ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2935 	if (ret_val)
2942 	return ret_val;
3003 	s32 ret_val = E1000_SUCCESS;
3020 	return ret_val;