dev/e1000/e1000_82571.c

95 	s32 ret_val;
165 	ret_val = e1000_get_phy_id_82571(hw);
166 	if (ret_val) {
168 		return ret_val;
176 			ret_val = -E1000_ERR_PHY;
180 			ret_val = -E1000_ERR_PHY;
185 			ret_val = -E1000_ERR_PHY;
188 		ret_val = -E1000_ERR_PHY;
192 	if (ret_val)
195 	return ret_val;
464 	s32 ret_val;
484 		ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
485 		if (ret_val)
486 			return ret_val;
490 		ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
491 		if (ret_val)
492 			return ret_val;
630 	s32 ret_val;
634 	ret_val = e1000_get_hw_semaphore(hw);
635 	if (ret_val)
636 		return ret_val;
642 		ret_val = e1000_acquire_nvm_generic(hw);
646 	if (ret_val)
649 	return ret_val;
681 	s32 ret_val;
689 		ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
693 		ret_val = e1000_write_nvm_spi(hw, offset, words, data);
696 		ret_val = -E1000_ERR_NVM;
700 	return ret_val;
714 	s32 ret_val;
719 	ret_val = e1000_update_nvm_checksum_generic(hw);
720 	if (ret_val)
721 		return ret_val;
801 	s32 ret_val = E1000_SUCCESS;
819 		ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
820 		if (ret_val)
825 		ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
826 		if (ret_val)
830 	return ret_val;
874 	s32 ret_val;
882 	ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
883 	if (ret_val)
884 		return ret_val;
888 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
890 		if (ret_val)
891 			return ret_val;
894 		ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
896 		if (ret_val)
897 			return ret_val;
899 		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
901 		if (ret_val)
902 			return ret_val;
905 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
913 			ret_val = phy->ops.read_reg(hw,
916 			if (ret_val)
917 				return ret_val;
920 			ret_val = phy->ops.write_reg(hw,
923 			if (ret_val)
924 				return ret_val;
926 			ret_val = phy->ops.read_reg(hw,
929 			if (ret_val)
930 				return ret_val;
933 			ret_val = phy->ops.write_reg(hw,
936 			if (ret_val)
937 				return ret_val;
953 	s32 ret_val;
960 	ret_val = e1000_disable_pcie_master_generic(hw);
961 	if (ret_val)
982 		ret_val = e1000_get_hw_semaphore_82574(hw);
999 		if (!ret_val)
1015 	ret_val = e1000_get_auto_rd_done_generic(hw);
1016 	if (ret_val)
1018 		return ret_val;
1050 		ret_val = e1000_check_alt_mac_addr_generic(hw);
1051 		if (ret_val)
1052 			return ret_val;
1074 	s32 ret_val;
1082 	ret_val = mac->ops.id_led_init(hw);
1084 	if (ret_val)
1106 	ret_val = mac->ops.setup_link(hw);
1141 	return ret_val;
1336 	s32 ret_val;
1340 	ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1341 	if (ret_val)
1385 	s32 ret_val;
1392 	ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1394 	if (ret_val)
1397 		ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1399 		if (ret_val)
1453 	s32 ret_val;
1465 		ret_val = e1000_copper_link_setup_m88(hw);
1468 		ret_val = e1000_copper_link_setup_igp(hw);
1475 	if (ret_val)
1476 		return ret_val;
1538 	s32 ret_val = E1000_SUCCESS;
1614 				ret_val =
1616 				if (ret_val) {
1680 	return ret_val;
1693 	s32 ret_val;
1697 	ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1698 	if (ret_val) {
1700 		return ret_val;
1778 	s32 ret_val;
1789 	ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1790 	if (ret_val)
1791 		return ret_val;
1801 		ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1802 		if (ret_val)
1803 			return ret_val;
1807 			ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1808 			if (ret_val)
1809 				return ret_val;
1810 			ret_val = nvm->ops.update(hw);
1811 			if (ret_val)
1812 				return ret_val;
1829 		s32 ret_val;
1835 		ret_val = e1000_check_alt_mac_addr_generic(hw);
1836 		if (ret_val)
1837 			return ret_val;