dev/e1000/e1000_82541.c

131 	struct e1000_nvm_info *nvm = &hw->nvm;
138 	switch (nvm->override) {
140 		nvm->type = e1000_nvm_eeprom_spi;
144 		nvm->type = e1000_nvm_eeprom_spi;
148 		nvm->type = e1000_nvm_eeprom_microwire;
152 		nvm->type = e1000_nvm_eeprom_microwire;
156 		nvm->type = eecd & E1000_EECD_TYPE ? e1000_nvm_eeprom_spi
161 	if (nvm->type == e1000_nvm_eeprom_spi) {
162 		nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ? 16 : 8;
163 		nvm->delay_usec = 1;
164 		nvm->opcode_bits = 8;
165 		nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) ? 32 : 8;
168 		nvm->ops.acquire	= e1000_acquire_nvm_generic;
169 		nvm->ops.read		= e1000_read_nvm_spi;
170 		nvm->ops.release	= e1000_release_nvm_generic;
171 		nvm->ops.update		= e1000_update_nvm_checksum_generic;
172 		nvm->ops.valid_led_default = e1000_valid_led_default_generic;
173 		nvm->ops.validate	= e1000_validate_nvm_checksum_generic;
174 		nvm->ops.write		= e1000_write_nvm_spi;
177 		 * nvm->word_size must be discovered after the pointers
178 		 * are set so we can verify the size from the nvm image
182 		nvm->word_size = 64;
183 		ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size);
194 			nvm->word_size = 1 << size;
197 		nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ? 8 : 6;
198 		nvm->delay_usec = 50;
199 		nvm->opcode_bits = 3;
200 		nvm->word_size = (eecd & E1000_EECD_ADDR_BITS) ? 256 : 64;
203 		nvm->ops.acquire	= e1000_acquire_nvm_generic;
204 		nvm->ops.read		= e1000_read_nvm_microwire;
205 		nvm->ops.release	= e1000_release_nvm_generic;
206 		nvm->ops.update		= e1000_update_nvm_checksum_generic;
207 		nvm->ops.valid_led_default = e1000_valid_led_default_generic;
208 		nvm->ops.validate	= e1000_validate_nvm_checksum_generic;
209 		nvm->ops.write		= e1000_write_nvm_microwire;
287 	hw->nvm.ops.init_params = e1000_init_nvm_params_82541;
1290 		ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);