dev/e1000/e1000_82541.c

89 	s32 ret_val;
111 	ret_val = e1000_get_phy_id(hw);
112 	if (ret_val)
117 		ret_val = -E1000_ERR_PHY;
122 	return ret_val;
132 	s32 ret_val = E1000_SUCCESS;
183 		ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size);
184 		if (ret_val)
213 	return ret_val;
380 	s32 ret_val;
385 	ret_val = mac->ops.id_led_init(hw);
386 	if (ret_val) {
392 	ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO,
394 	if (ret_val)
418 	ret_val = mac->ops.setup_link(hw);
434 	return ret_val;
449 	s32 ret_val;
454 	ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
455 	if (ret_val)
467 	ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data);
468 	if (ret_val)
474 		ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data);
475 		if (ret_val)
488 	return ret_val;
502 	s32 ret_val;
507 	ret_val = e1000_phy_hw_reset_generic(hw);
508 	if (ret_val)
522 	return ret_val;
538 	s32  ret_val;
557 	ret_val = e1000_copper_link_setup_igp(hw);
558 	if (ret_val)
572 	ret_val = e1000_setup_copper_link_generic(hw);
575 	return ret_val;
588 	s32 ret_val;
600 		ret_val = E1000_SUCCESS;
609 	ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
610 	if (ret_val)
614 		ret_val = e1000_config_dsp_after_link_change_82541(hw, false);
631 		ret_val = -E1000_ERR_CONFIG;
635 	ret_val = e1000_config_dsp_after_link_change_82541(hw, true);
650 	ret_val = e1000_config_fc_after_link_up_generic(hw);
651 	if (ret_val)
655 	return ret_val;
674 	s32 ret_val;
687 		ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
688 		if (ret_val) {
694 			ret_val = E1000_SUCCESS;
698 		ret_val = phy->ops.get_cable_length(hw);
699 		if (ret_val)
706 				ret_val = phy->ops.read_reg(hw,
709 				if (ret_val)
714 				ret_val = phy->ops.write_reg(hw,
717 				if (ret_val)
725 			ret_val = E1000_SUCCESS;
730 		ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
731 		if (ret_val)
736 			ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS,
738 			if (ret_val)
745 				ret_val = phy->ops.write_reg(hw,
748 				if (ret_val)
763 			ret_val = phy->ops.read_reg(hw, 0x2F5B,
765 			if (ret_val)
769 			ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
770 			if (ret_val)
775 			ret_val = phy->ops.write_reg(hw, 0x0000,
777 			if (ret_val)
780 				ret_val = phy->ops.read_reg(hw,
783 				if (ret_val)
789 				ret_val = phy->ops.write_reg(hw,
792 				if (ret_val)
796 			ret_val = phy->ops.write_reg(hw, 0x0000,
798 			if (ret_val)
804 			ret_val = phy->ops.write_reg(hw, 0x2F5B,
806 			if (ret_val)
813 			ret_val = E1000_SUCCESS;
821 		ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data);
822 		if (ret_val)
826 		ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
827 		if (ret_val)
832 		ret_val = phy->ops.write_reg(hw, 0x0000,
834 		if (ret_val)
837 		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_DSP_FFE,
839 		if (ret_val)
842 		ret_val = phy->ops.write_reg(hw, 0x0000,
844 		if (ret_val)
850 		ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data);
852 		if (ret_val)
859 	return ret_val;
876 	s32 ret_val = E1000_SUCCESS;
889 		ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data);
890 		if (ret_val)
898 			ret_val = -E1000_ERR_PHY;
929 	return ret_val;
949 	s32 ret_val;
959 		ret_val = e1000_set_d3_lplu_state_generic(hw, active);
964 	ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data);
965 	if (ret_val)
970 		ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
971 		if (ret_val)
981 			ret_val = phy->ops.read_reg(hw,
984 			if (ret_val)
988 			ret_val = phy->ops.write_reg(hw,
991 			if (ret_val)
994 			ret_val = phy->ops.read_reg(hw,
997 			if (ret_val)
1001 			ret_val = phy->ops.write_reg(hw,
1004 			if (ret_val)
1011 		ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
1012 		if (ret_val)
1016 		ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1018 		if (ret_val)
1022 		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1027 	return ret_val;
1040 	s32 ret_val;
1044 	ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO,
1046 	if (ret_val)
1049 	ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO,
1052 	if (ret_val)
1058 	return ret_val;
1071 	s32 ret_val;
1075 	ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO,
1077 	if (ret_val)
1083 	return ret_val;
1095 	u32 ret_val;
1101 		ret_val = E1000_SUCCESS;
1112 	ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data);
1194 	return ret_val;
1283 	s32  ret_val = E1000_SUCCESS;
1290 		ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
1291 		if (ret_val) {
1303 	return ret_val;