dev/e1000/e1000_82540.c

49 static s32  e1000_init_phy_params_82540(struct e1000_hw *hw);
50 static s32  e1000_init_nvm_params_82540(struct e1000_hw *hw);
51 static s32  e1000_init_mac_params_82540(struct e1000_hw *hw);
52 static s32  e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw);
53 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw);
54 static s32  e1000_init_hw_82540(struct e1000_hw *hw);
55 static s32  e1000_reset_hw_82540(struct e1000_hw *hw);
56 static s32  e1000_set_phy_mode_82540(struct e1000_hw *hw);
57 static s32  e1000_set_vco_speed_82540(struct e1000_hw *hw);
58 static s32  e1000_setup_copper_link_82540(struct e1000_hw *hw);
59 static s32  e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw);
60 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw);
61 static s32  e1000_read_mac_addr_82540(struct e1000_hw *hw);
65  * @hw: pointer to the HW structure
67 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw)
69 	struct e1000_phy_info *phy = &hw->phy;
90 	ret_val = e1000_get_phy_id(hw);
95 	switch (hw->mac.type) {
116  * @hw: pointer to the HW structure
118 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw)
120 	struct e1000_nvm_info *nvm = &hw->nvm;
121 	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
157  * @hw: pointer to the HW structure
159 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw)
161 	struct e1000_mac_info *mac = &hw->mac;
167 	switch (hw->device_id) {
172 		hw->phy.media_type = e1000_media_type_fiber;
176 		hw->phy.media_type = e1000_media_type_internal_serdes;
179 		hw->phy.media_type = e1000_media_type_copper;
196 	/* hw initialization */
202 		(hw->phy.media_type == e1000_media_type_copper)
206 	switch (hw->phy.media_type) {
223 		(hw->phy.media_type == e1000_media_type_copper)
252  * @hw: pointer to the HW structure
256 void e1000_init_function_pointers_82540(struct e1000_hw *hw)
260 	hw->mac.ops.init_params = e1000_init_mac_params_82540;
261 	hw->nvm.ops.init_params = e1000_init_nvm_params_82540;
262 	hw->phy.ops.init_params = e1000_init_phy_params_82540;
267  *  @hw: pointer to the HW structure
271 static s32 e1000_reset_hw_82540(struct e1000_hw *hw)
279 	E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
281 	E1000_WRITE_REG(hw, E1000_RCTL, 0);
282 	E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
283 	E1000_WRITE_FLUSH(hw);
291 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
294 	switch (hw->mac.type) {
297 		E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST);
305 		E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
313 	manc = E1000_READ_REG(hw, E1000_MANC);
315 	E1000_WRITE_REG(hw, E1000_MANC, manc);
317 	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
318 	E1000_READ_REG(hw, E1000_ICR);
325  *  @hw: pointer to the HW structure
329 static s32 e1000_init_hw_82540(struct e1000_hw *hw)
331 	struct e1000_mac_info *mac = &hw->mac;
339 	ret_val = mac->ops.id_led_init(hw);
348 		E1000_WRITE_REG(hw, E1000_VET, 0);
350 	mac->ops.clear_vfta(hw);
353 	e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
358 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
367 		E1000_WRITE_FLUSH(hw);
371 		e1000_pcix_mmrbc_workaround_generic(hw);
374 	ret_val = mac->ops.setup_link(hw);
376 	txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
379 	E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
387 	e1000_clear_hw_cntrs_82540(hw);
389 	if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) ||
390 	    (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) {
391 		ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
397 		E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
405  *  @hw: pointer to the HW structure
412 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw)
420 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
423 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
425 	ret_val = e1000_set_phy_mode_82540(hw);
429 	if (hw->mac.type == e1000_82545_rev_3 ||
430 	    hw->mac.type == e1000_82546_rev_3) {
431 		ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
436 		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
442 	ret_val = e1000_copper_link_setup_m88(hw);
446 	ret_val = e1000_setup_copper_link_generic(hw);
454  *  @hw: pointer to the HW structure
461 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw)
463 	struct e1000_mac_info *mac = &hw->mac;
471 		if (hw->phy.media_type == e1000_media_type_internal_serdes) {
476 			ret_val = e1000_adjust_serdes_amplitude_82540(hw);
481 		ret_val = e1000_set_vco_speed_82540(hw);
488 	ret_val = e1000_setup_fiber_serdes_link_generic(hw);
496  *  @hw: pointer to the HW structure
500 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
507 	ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data);
514 		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_EXT_CTRL,
526  *  @hw: pointer to the HW structure
530 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
540 	ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_PAGE_SELECT,
545 	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
549 	ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
554 	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
560 	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
564 	ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
569 	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
573 	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
582  *  @hw: pointer to the HW structure
589 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
596 	if (hw->mac.type != e1000_82545_rev_3)
599 	ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data);
606 		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
612 		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL,
627  * @hw: pointer to the HW structure
632 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw)
635 	if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
636 		e1000_power_down_phy_copper(hw);
643  *  @hw: pointer to the HW structure
647 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw)
651 	e1000_clear_hw_cntrs_base_generic(hw);
653 	E1000_READ_REG(hw, E1000_PRC64);
654 	E1000_READ_REG(hw, E1000_PRC127);
655 	E1000_READ_REG(hw, E1000_PRC255);
656 	E1000_READ_REG(hw, E1000_PRC511);
657 	E1000_READ_REG(hw, E1000_PRC1023);
658 	E1000_READ_REG(hw, E1000_PRC1522);
659 	E1000_READ_REG(hw, E1000_PTC64);
660 	E1000_READ_REG(hw, E1000_PTC127);
661 	E1000_READ_REG(hw, E1000_PTC255);
662 	E1000_READ_REG(hw, E1000_PTC511);
663 	E1000_READ_REG(hw, E1000_PTC1023);
664 	E1000_READ_REG(hw, E1000_PTC1522);
666 	E1000_READ_REG(hw, E1000_ALGNERRC);
667 	E1000_READ_REG(hw, E1000_RXERRC);
668 	E1000_READ_REG(hw, E1000_TNCRS);
669 	E1000_READ_REG(hw, E1000_CEXTERR);
670 	E1000_READ_REG(hw, E1000_TSCTC);
671 	E1000_READ_REG(hw, E1000_TSCTFC);
673 	E1000_READ_REG(hw, E1000_MGTPRC);
674 	E1000_READ_REG(hw, E1000_MGTPDC);
675 	E1000_READ_REG(hw, E1000_MGTPTC);
680  *  @hw: pointer to the HW structure
692 s32 e1000_read_mac_addr_82540(struct e1000_hw *hw)
701 		ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
706 		hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
707 		hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
711 	if (hw->bus.func == E1000_FUNC_1)
712 		hw->mac.perm_addr[5] ^= 1;
715 		hw->mac.addr[i] = hw->mac.perm_addr[i];