Lines Matching refs:hw
42 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
43 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
44 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
45 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
46 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
49 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
52 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
54 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
55 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
56 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
57 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
59 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
60 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw);
61 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
62 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
63 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
64 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
65 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
66 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
68 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
70 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
71 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
72 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
86 * @hw: pointer to the HW structure
88 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
90 struct e1000_phy_info *phy = &hw->phy;
95 if (hw->phy.media_type != e1000_media_type_copper) {
126 ret_val = e1000_get_phy_id(hw);
137 * @hw: pointer to the HW structure
139 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
141 struct e1000_nvm_info *nvm = &hw->nvm;
142 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
193 * @hw: pointer to the HW structure
195 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
197 struct e1000_mac_info *mac = &hw->mac;
202 switch (hw->device_id) {
204 hw->phy.media_type = e1000_media_type_internal_serdes;
210 hw->phy.media_type = e1000_media_type_copper;
226 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
237 /* hw initialization */
268 hw->mac.ops.set_lan_id(hw);
275 * @hw: pointer to the HW structure
279 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
283 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;
284 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;
285 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
290 * @hw: pointer to the HW structure
294 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
300 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
301 return e1000_acquire_swfw_sync(hw, mask);
306 * @hw: pointer to the HW structure
310 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
316 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
317 e1000_release_swfw_sync(hw, mask);
322 * @hw: pointer to the HW structure
327 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
335 return e1000_acquire_swfw_sync(hw, mask);
340 * @hw: pointer to the HW structure
344 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
352 e1000_release_swfw_sync(hw, mask);
357 * @hw: pointer to the HW structure
361 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
367 ret_val = e1000_acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
371 ret_val = e1000_acquire_nvm_generic(hw);
374 e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM);
381 * @hw: pointer to the HW structure
385 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
389 e1000_release_nvm_generic(hw);
390 e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM);
395 * @hw: pointer to the HW structure
401 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
410 ret_val = e1000_acquire_phy_80003es2lan(hw);
425 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
427 e1000_release_phy_80003es2lan(hw);
431 if (hw->dev_spec._80003es2lan.mdic_wa_enable) {
439 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
442 e1000_release_phy_80003es2lan(hw);
448 ret_val = e1000_read_phy_reg_mdic(hw,
454 ret_val = e1000_read_phy_reg_mdic(hw,
459 e1000_release_phy_80003es2lan(hw);
466 * @hw: pointer to the HW structure
472 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
481 ret_val = e1000_acquire_phy_80003es2lan(hw);
496 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
498 e1000_release_phy_80003es2lan(hw);
502 if (hw->dev_spec._80003es2lan.mdic_wa_enable) {
510 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
513 e1000_release_phy_80003es2lan(hw);
519 ret_val = e1000_write_phy_reg_mdic(hw,
525 ret_val = e1000_write_phy_reg_mdic(hw,
530 e1000_release_phy_80003es2lan(hw);
537 * @hw: pointer to the HW structure
544 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
549 return e1000_write_nvm_spi(hw, offset, words, data);
554 * @hw: pointer to the HW structure
559 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
566 if (hw->bus.func == 1)
570 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
585 * @hw: pointer to the HW structure
590 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
598 if (!(hw->phy.ops.read_reg))
604 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
609 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
615 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
619 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
624 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
630 if (hw->phy.autoneg_wait_to_complete) {
633 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
642 ret_val = e1000_phy_reset_dsp_generic(hw);
648 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
654 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
663 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
672 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
680 * @hw: pointer to the HW structure
685 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
687 struct e1000_phy_info *phy = &hw->phy;
693 if (!(hw->phy.ops.read_reg))
696 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
715 * @hw: pointer to the HW structure
721 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
728 if (hw->phy.media_type == e1000_media_type_copper) {
729 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
731 hw->phy.ops.cfg_on_link_up(hw);
733 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
743 * @hw: pointer to the HW structure
747 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
758 ret_val = e1000_disable_pcie_master_generic(hw);
763 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
765 E1000_WRITE_REG(hw, E1000_RCTL, 0);
766 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
767 E1000_WRITE_FLUSH(hw);
771 ctrl = E1000_READ_REG(hw, E1000_CTRL);
773 ret_val = e1000_acquire_phy_80003es2lan(hw);
778 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
779 e1000_release_phy_80003es2lan(hw);
782 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
786 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
794 ret_val = e1000_get_auto_rd_done_generic(hw);
800 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
801 E1000_READ_REG(hw, E1000_ICR);
803 return e1000_check_alt_mac_addr_generic(hw);
808 * @hw: pointer to the HW structure
810 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
812 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
814 struct e1000_mac_info *mac = &hw->mac;
822 e1000_initialize_hw_bits_80003es2lan(hw);
825 ret_val = mac->ops.id_led_init(hw);
832 mac->ops.clear_vfta(hw);
835 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
840 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
843 ret_val = mac->ops.setup_link(hw);
849 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
853 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
862 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
865 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
868 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
871 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
874 reg_data = E1000_READ_REG(hw, E1000_TCTL);
876 E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
879 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT);
882 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data);
885 reg_data = E1000_READ_REG(hw, E1000_TIPG);
888 E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
890 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
892 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
895 hw->dev_spec._80003es2lan.mdic_wa_enable = true;
898 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>
903 hw->dev_spec._80003es2lan.mdic_wa_enable = false;
911 e1000_clear_hw_cntrs_80003es2lan(hw);
917 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
918 * @hw: pointer to the HW structure
922 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
929 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
931 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
934 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
936 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
939 reg = E1000_READ_REG(hw, E1000_TARC(0));
941 if (hw->phy.media_type != e1000_media_type_copper)
943 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
946 reg = E1000_READ_REG(hw, E1000_TARC(1));
947 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
951 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
956 reg = E1000_READ_REG(hw, E1000_RFCTL);
958 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
965 * @hw: pointer to the HW structure
969 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
971 struct e1000_phy_info *phy = &hw->phy;
978 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
986 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
997 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
1026 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1031 ret_val = hw->phy.ops.commit(hw);
1041 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
1046 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
1050 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
1054 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1059 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1063 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1065 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1067 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1075 if (!hw->mac.ops.check_mng_mode(hw)) {
1078 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1083 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1089 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1098 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1103 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1112 * @hw: pointer to the HW structure
1117 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1125 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1128 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1134 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1138 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1143 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1148 e1000_read_kmrn_reg_80003es2lan(hw,
1155 e1000_write_kmrn_reg_80003es2lan(hw,
1161 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1165 return e1000_setup_copper_link_generic(hw);
1170 * @hw: pointer to the HW structure
1175 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1183 if (hw->phy.media_type == e1000_media_type_copper) {
1184 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed,
1190 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1192 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1200 * @hw: pointer to the HW structure
1206 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1217 e1000_write_kmrn_reg_80003es2lan(hw,
1224 tipg = E1000_READ_REG(hw, E1000_TIPG);
1227 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1230 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1235 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1247 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1252 * @hw: pointer to the HW structure
1257 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1268 e1000_write_kmrn_reg_80003es2lan(hw,
1275 tipg = E1000_READ_REG(hw, E1000_TIPG);
1278 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1281 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1286 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1295 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1300 * @hw: pointer to the HW structure
1308 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1316 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1322 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1323 E1000_WRITE_FLUSH(hw);
1327 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
1330 e1000_release_mac_csr_80003es2lan(hw);
1337 * @hw: pointer to the HW structure
1345 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1353 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1359 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1360 E1000_WRITE_FLUSH(hw);
1364 e1000_release_mac_csr_80003es2lan(hw);
1371 * @hw: pointer to the HW structure
1373 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1383 ret_val = e1000_check_alt_mac_addr_generic(hw);
1387 return e1000_read_mac_addr_generic(hw);
1392 * @hw: pointer to the HW structure
1397 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1400 if (!(hw->mac.ops.check_mng_mode(hw) ||
1401 hw->phy.ops.check_reset_block(hw)))
1402 e1000_power_down_phy_copper(hw);
1409 * @hw: pointer to the HW structure
1413 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1417 e1000_clear_hw_cntrs_base_generic(hw);
1419 E1000_READ_REG(hw, E1000_PRC64);
1420 E1000_READ_REG(hw, E1000_PRC127);
1421 E1000_READ_REG(hw, E1000_PRC255);
1422 E1000_READ_REG(hw, E1000_PRC511);
1423 E1000_READ_REG(hw, E1000_PRC1023);
1424 E1000_READ_REG(hw, E1000_PRC1522);
1425 E1000_READ_REG(hw, E1000_PTC64);
1426 E1000_READ_REG(hw, E1000_PTC127);
1427 E1000_READ_REG(hw, E1000_PTC255);
1428 E1000_READ_REG(hw, E1000_PTC511);
1429 E1000_READ_REG(hw, E1000_PTC1023);
1430 E1000_READ_REG(hw, E1000_PTC1522);
1432 E1000_READ_REG(hw, E1000_ALGNERRC);
1433 E1000_READ_REG(hw, E1000_RXERRC);
1434 E1000_READ_REG(hw, E1000_TNCRS);
1435 E1000_READ_REG(hw, E1000_CEXTERR);
1436 E1000_READ_REG(hw, E1000_TSCTC);
1437 E1000_READ_REG(hw, E1000_TSCTFC);
1439 E1000_READ_REG(hw, E1000_MGTPRC);
1440 E1000_READ_REG(hw, E1000_MGTPDC);
1441 E1000_READ_REG(hw, E1000_MGTPTC);
1443 E1000_READ_REG(hw, E1000_IAC);
1444 E1000_READ_REG(hw, E1000_ICRXOC);
1446 E1000_READ_REG(hw, E1000_ICRXPTC);
1447 E1000_READ_REG(hw, E1000_ICRXATC);
1448 E1000_READ_REG(hw, E1000_ICTXPTC);
1449 E1000_READ_REG(hw, E1000_ICTXATC);
1450 E1000_READ_REG(hw, E1000_ICTXQEC);
1451 E1000_READ_REG(hw, E1000_ICTXQMTC);
1452 E1000_READ_REG(hw, E1000_ICRXDMTC);