Lines Matching defs:ret_val
91 s32 ret_val;
126 ret_val = e1000_get_phy_id(hw);
132 return ret_val;
363 s32 ret_val;
367 ret_val = e1000_acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
368 if (ret_val)
369 return ret_val;
371 ret_val = e1000_acquire_nvm_generic(hw);
373 if (ret_val)
376 return ret_val;
404 s32 ret_val;
410 ret_val = e1000_acquire_phy_80003es2lan(hw);
411 if (ret_val)
412 return ret_val;
425 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
426 if (ret_val) {
428 return ret_val;
439 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
448 ret_val = e1000_read_phy_reg_mdic(hw,
454 ret_val = e1000_read_phy_reg_mdic(hw,
461 return ret_val;
475 s32 ret_val;
481 ret_val = e1000_acquire_phy_80003es2lan(hw);
482 if (ret_val)
483 return ret_val;
496 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
497 if (ret_val) {
499 return ret_val;
510 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
519 ret_val = e1000_write_phy_reg_mdic(hw,
525 ret_val = e1000_write_phy_reg_mdic(hw,
532 return ret_val;
592 s32 ret_val;
604 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
605 if (ret_val)
606 return ret_val;
609 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
610 if (ret_val)
611 return ret_val;
615 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
616 if (ret_val)
617 return ret_val;
624 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
625 if (ret_val)
626 return ret_val;
633 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
635 if (ret_val)
636 return ret_val;
642 ret_val = e1000_phy_reset_dsp_generic(hw);
643 if (ret_val)
644 return ret_val;
648 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
650 if (ret_val)
651 return ret_val;
654 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
656 if (ret_val)
657 return ret_val;
672 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
675 return ret_val;
688 s32 ret_val;
696 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
697 if (ret_val)
698 return ret_val;
724 s32 ret_val;
729 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
733 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
738 return ret_val;
750 s32 ret_val;
758 ret_val = e1000_disable_pcie_master_generic(hw);
759 if (ret_val)
773 ret_val = e1000_acquire_phy_80003es2lan(hw);
774 if (ret_val)
775 return ret_val;
782 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
784 if (!ret_val) {
786 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
789 if (ret_val)
794 ret_val = e1000_get_auto_rd_done_generic(hw);
795 if (ret_val)
797 return ret_val;
816 s32 ret_val;
825 ret_val = mac->ops.id_led_init(hw);
827 if (ret_val)
843 ret_val = mac->ops.setup_link(hw);
844 if (ret_val)
845 return ret_val;
848 ret_val =
851 if (!ret_val) {
853 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
856 if (ret_val)
897 ret_val =
900 if (!ret_val) {
913 return ret_val;
972 s32 ret_val;
978 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
979 if (ret_val)
980 return ret_val;
986 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
987 if (ret_val)
988 return ret_val;
997 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
998 if (ret_val)
999 return ret_val;
1026 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1027 if (ret_val)
1028 return ret_val;
1031 ret_val = hw->phy.ops.commit(hw);
1032 if (ret_val) {
1034 return ret_val;
1041 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
1042 if (ret_val)
1043 return ret_val;
1046 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
1047 if (ret_val)
1048 return ret_val;
1050 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
1051 if (ret_val)
1052 return ret_val;
1054 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1055 if (ret_val)
1056 return ret_val;
1059 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1060 if (ret_val)
1061 return ret_val;
1067 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1068 if (ret_val)
1069 return ret_val;
1078 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1080 if (ret_val)
1081 return ret_val;
1083 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1085 if (ret_val)
1086 return ret_val;
1089 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1091 if (ret_val)
1092 return ret_val;
1098 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1099 if (ret_val)
1100 return ret_val;
1103 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1104 if (ret_val)
1105 return ret_val;
1120 s32 ret_val;
1134 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1136 if (ret_val)
1137 return ret_val;
1138 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1140 if (ret_val)
1141 return ret_val;
1143 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1145 if (ret_val)
1146 return ret_val;
1147 ret_val =
1151 if (ret_val)
1152 return ret_val;
1154 ret_val =
1158 if (ret_val)
1159 return ret_val;
1161 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1162 if (ret_val)
1163 return ret_val;
1177 s32 ret_val = E1000_SUCCESS;
1184 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed,
1186 if (ret_val)
1187 return ret_val;
1190 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1192 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1195 return ret_val;
1208 s32 ret_val;
1216 ret_val =
1220 if (ret_val)
1221 return ret_val;
1230 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1232 if (ret_val)
1233 return ret_val;
1235 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1237 if (ret_val)
1238 return ret_val;
1259 s32 ret_val;
1267 ret_val =
1271 if (ret_val)
1272 return ret_val;
1281 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1283 if (ret_val)
1284 return ret_val;
1286 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1288 if (ret_val)
1289 return ret_val;
1312 s32 ret_val;
1316 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1317 if (ret_val)
1318 return ret_val;
1332 return ret_val;
1349 s32 ret_val;
1353 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1354 if (ret_val)
1355 return ret_val;
1366 return ret_val;
1375 s32 ret_val;
1383 ret_val = e1000_check_alt_mac_addr_generic(hw);
1384 if (ret_val)
1385 return ret_val;