Lines Matching refs:nvm

22 	struct igc_nvm_info *nvm = &hw->nvm;
26 nvm->ops.init_params = igc_null_ops_generic;
27 nvm->ops.acquire = igc_null_ops_generic;
28 nvm->ops.read = igc_null_read_nvm;
29 nvm->ops.release = igc_null_nvm_generic;
30 nvm->ops.reload = igc_reload_nvm_generic;
31 nvm->ops.update = igc_null_ops_generic;
32 nvm->ops.validate = igc_null_ops_generic;
33 nvm->ops.write = igc_null_write_nvm;
88 usec_delay(hw->nvm.delay_usec);
103 usec_delay(hw->nvm.delay_usec);
118 struct igc_nvm_info *nvm = &hw->nvm;
125 if (nvm->type == igc_nvm_eeprom_spi)
137 usec_delay(nvm->delay_usec);
263 struct igc_nvm_info *nvm = &hw->nvm;
268 if (nvm->type == igc_nvm_eeprom_spi) {
273 usec_delay(nvm->delay_usec);
277 usec_delay(nvm->delay_usec);
294 if (hw->nvm.type == igc_nvm_eeprom_spi) {
328 struct igc_nvm_info *nvm = &hw->nvm;
334 if (nvm->type == igc_nvm_eeprom_spi) {
350 hw->nvm.opcode_bits);
380 struct igc_nvm_info *nvm = &hw->nvm;
389 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
391 DEBUGOUT("nvm parameter(s) out of bounds\n");
428 struct igc_nvm_info *nvm = &hw->nvm;
437 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
439 DEBUGOUT("nvm parameter(s) out of bounds\n");
446 ret_val = nvm->ops.acquire(hw);
452 nvm->ops.release(hw);
460 nvm->opcode_bits);
467 if ((nvm->address_bits == 8) && (offset >= 128))
471 igc_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
473 nvm->address_bits);
482 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
488 nvm->ops.release(hw);
519 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
525 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
570 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
591 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
653 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
686 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
694 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);