dev/igc/igc_i225.c

29 	struct igc_nvm_info *nvm = &hw->nvm;
49 	nvm->word_size = 1 << size;
50 	nvm->opcode_bits = 8;
51 	nvm->delay_usec = 1;
52 	nvm->type = igc_nvm_eeprom_spi;
55 	nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8;
56 	nvm->address_bits = eecd & IGC_EECD_ADDR_BITS ?
59 	if (nvm->word_size == (1 << 15))
60 		nvm->page_size = 128;
62 	nvm->ops.acquire = igc_acquire_nvm_i225;
63 	nvm->ops.release = igc_release_nvm_i225;
65 		hw->nvm.type = igc_nvm_flash_hw;
66 		nvm->ops.read    = igc_read_nvm_srrd_i225;
67 		nvm->ops.write   = igc_write_nvm_srwr_i225;
68 		nvm->ops.validate = igc_validate_nvm_checksum_i225;
69 		nvm->ops.update   = igc_update_nvm_checksum_i225;
71 		hw->nvm.type = igc_nvm_invm;
72 		nvm->ops.write    = igc_null_write_nvm;
73 		nvm->ops.validate = igc_null_ops_generic;
74 		nvm->ops.update   = igc_null_ops_generic;
376 	s32 timeout = hw->nvm.word_size + 1;
461 		if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
464 			hw->nvm.ops.release(hw);
506 		if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
509 			hw->nvm.ops.release(hw);
535 	struct igc_nvm_info *nvm = &hw->nvm;
545 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
547 		DEBUGOUT("nvm parameter(s) out of bounds\n");
591 	if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
596 		read_op_ptr = hw->nvm.ops.read;
597 		hw->nvm.ops.read = igc_read_nvm_eerd;
602 		hw->nvm.ops.read = read_op_ptr;
604 		hw->nvm.ops.release(hw);
637 	if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
638 		/* Do not use hw->nvm.ops.write, hw->nvm.ops.read
646 				hw->nvm.ops.release(hw);
657 			hw->nvm.ops.release(hw);
662 		hw->nvm.ops.release(hw);
1077 	hw->nvm.ops.init_params = igc_init_nvm_params_i225;