dev/igc/igc_i225.c

138 	s32 ret_val = IGC_SUCCESS;
167 	ret_val = hw->phy.ops.reset(hw);
168 	if (ret_val)
171 	ret_val = igc_get_phy_id(hw);
175 	return ret_val;
187 	s32 ret_val;
195 	ret_val = igc_disable_pcie_master_generic(hw);
196 	if (ret_val)
213 	ret_val = igc_get_auto_rd_done_generic(hw);
214 	if (ret_val) {
228 	ret_val = igc_check_alt_mac_addr_generic(hw);
230 	return ret_val;
243 	s32 ret_val;
247 	ret_val = igc_acquire_swfw_sync_i225(hw, IGC_SWFW_EEP_SM);
249 	return ret_val;
277 	s32 ret_val = IGC_SUCCESS;
284 			ret_val = -IGC_ERR_SWFW_SYNC;
302 		ret_val = -IGC_ERR_SWFW_SYNC;
312 	return ret_val;
349 	s32 ret_val;
363 	ret_val = igc_setup_copper_link_generic(hw);
365 	return ret_val;
538 	s32 ret_val = IGC_SUCCESS;
548 		ret_val = -IGC_ERR_NVM;
562 				ret_val = IGC_SUCCESS;
568 		if (ret_val != IGC_SUCCESS) {
575 	return ret_val;
621 	s32 ret_val;
631 	ret_val = igc_read_nvm_eerd(hw, 0, 1, &nvm_data);
632 	if (ret_val != IGC_SUCCESS) {
644 			ret_val = igc_read_nvm_eerd(hw, i, 1, &nvm_data);
645 			if (ret_val) {
654 		ret_val = __igc_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1,
656 		if (ret_val != IGC_SUCCESS) {
664 		ret_val = igc_update_flash_i225(hw);
666 		ret_val = IGC_ERR_SWFW_SYNC;
669 	return ret_val;
678 	bool ret_val = false;
685 		ret_val = true;
687 	return ret_val;
699 	s32 ret_val = IGC_SUCCESS;
708 		ret_val = IGC_ERR_INVALID_ARGUMENT;
711 	return ret_val;
726 	s32 ret_val = IGC_SUCCESS;
753 		ret_val = IGC_ERR_INVALID_ARGUMENT;
756 	return ret_val;
774 	s32 ret_val = 0;
784 		ret_val = igc_pool_flash_update_done_i225(hw);
785 		if (ret_val == -IGC_ERR_NVM) {
793 		ret_val = igc_pool_flash_update_done_i225(hw);
794 		if (ret_val == IGC_SUCCESS)
809 		ret_val = igc_write_erase_flash_command_i225(hw,
812 		if (!ret_val) {
822 			ret_val = igc_set_flsw_flash_burst_counter_i225(hw,
824 			if (ret_val != IGC_SUCCESS)
828 			ret_val = igc_write_erase_flash_command_i225(hw,
831 			if (ret_val != IGC_SUCCESS)
834 			ret_val = igc_read_nvm_eerd(hw, current_offset,
836 			if (ret_val) {
847 			ret_val = igc_poll_eerd_eewr_done(hw,
849 			if (ret_val)
856 	return ret_val;
864 	s32 ret_val = -IGC_ERR_NVM;
872 			ret_val = IGC_SUCCESS;
878 	return ret_val;
993 	s32 ret_val;
1004 		ret_val = IGC_SUCCESS;
1012 	ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
1013 	if (ret_val)
1023 	ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
1024 	if (ret_val)
1054 	ret_val = igc_config_fc_after_link_up_generic(hw);
1055 	if (ret_val)
1061 	ret_val = igc_set_ltr_i225(hw, link);
1063 	return ret_val;
1088 	s32 ret_val;
1092 	ret_val = igc_init_hw_base(hw);
1093 	return ret_val;