graphics/radeon/vip.c

32 	vuint8 *regs = di->regs;
36 	OUTREG( regs, RADEON_VIPH_REG_ADDR, (channel << 14) | address | 0x2000 );
43 	OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, 0,
48 	INREG( regs, RADEON_VIPH_REG_DATA );
57 	OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS,
62 	*data = INREG( regs, RADEON_VIPH_REG_DATA );
72 	OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS,
99    	vuint8 *regs = di->regs;
113 	OUTREG( regs, RADEON_VIPH_REG_ADDR,  (channel << 14) | address | 0x3000);
126 	OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT,
127 		INREG( regs, RADEON_VIPH_TIMEOUT_STAT) &
134 	INREG( regs, RADEON_VIPH_REG_DATA);
143 	tmp = INREG( regs, RADEON_VIPH_TIMEOUT_STAT);
144 	OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (tmp & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS);
150 	        *buffer=(uint8)(INREG( regs, RADEON_VIPH_REG_DATA) & 0xff);
153 	        *(uint16 *)buffer=(uint16) (INREG( regs, RADEON_VIPH_REG_DATA) & 0xffff);
156 	        *(uint32 *)buffer=(uint32) ( INREG( regs, RADEON_VIPH_REG_DATA) & 0xffffffff);
165 	OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT,
166 		(INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS);
192 	vuint8 *regs = di->regs;
195 	OUTREG( regs, RADEON_VIPH_REG_ADDR, (channel << 14) | (address & ~0x2000) );
202 	OUTREG( regs, RADEON_VIPH_REG_DATA, data );
230 	vuint8 *regs = di->regs;
239 	OUTREG( regs, RADEON_VIPH_REG_ADDR,
257 		OUTREG( regs, RADEON_VIPH_REG_DATA, *(uint32*)(buffer + i));
296 	vuint8 *regs = di->regs;
309 	    OUTREG( regs, RADEON_VIPH_CONTROL, 4 | 	(15 << RADEON_VIPH_CONTROL_VIPH_MAX_WAIT_SHIFT) |
311 	    OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) |
313 	    OUTREG( regs, RADEON_VIPH_DV_LAT,
319 	    OUTREG( regs, RADEON_VIPH_DMA_CHUNK, 0x151);
320 	    OUTREG( regs, RADEON_TEST_DEBUG_CNTL, INREG( regs, RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL_OUT_EN));
322 		    OUTREG( regs, RADEON_VIPH_CONTROL, 9 | 	(15 << RADEON_VIPH_CONTROL_VIPH_MAX_WAIT_SHIFT) |
324 	    OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) |
326 	    OUTREG( regs, RADEON_VIPH_DV_LAT,
332 	    OUTREG( regs, RADEON_VIPH_DMA_CHUNK, 0x0);
333 	    OUTREG( regs, RADEON_TEST_DEBUG_CNTL, INREG( regs, RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL_OUT_EN));
348 	vuint8 *regs = di->regs;
354 	timeout = INREG( regs, RADEON_VIPH_TIMEOUT_STAT );
357 		OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT,
359 		return (INREG( regs, RADEON_VIPH_CONTROL) & 0x2000) ? B_BUSY : B_ERROR;
361 	return (INREG( regs, RADEON_VIPH_CONTROL) & 0x2000) ? B_BUSY : B_OK;
366 	vuint8 *regs = di->regs;
369 	timeout = INREG( regs, RADEON_VIPH_TIMEOUT_STAT);
372 		OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (timeout & 0xfffffff0) | channel);
373 		return (INREG( regs, RADEON_VIPH_CONTROL) & 0x2000) ? B_BUSY : B_ERROR;
375 	return (INREG( regs, RADEON_VIPH_CONTROL) & 0x2000) ? B_BUSY : B_OK ;