graphics/radeon/vip.c

23 static bool Radeon_VIPWaitForIdle( device_info *di );
24 static status_t RADEON_VIPFifoIdle(device_info *di, uint8 channel);
30 	device_info *di, uint channel, uint address, uint32 *data )
32 	vuint8 *regs = di->regs;
34 	Radeon_WaitForFifo( di, 2 );
38 	if( !Radeon_VIPWaitForIdle( di ))
42 	Radeon_WaitForFifo( di, 2 );
45 	//Radeon_WaitForIdle( di, false, false );
50 	if( !Radeon_VIPWaitForIdle( di ))
53 	//Radeon_WaitForIdle( di, false, false );
56 	Radeon_WaitForFifo( di, 2 );
59 	//Radeon_WaitForIdle( di, false, false );
66 	if( !Radeon_VIPWaitForIdle( di ))
71 	Radeon_WaitForFifo( di, 2 );
80 	device_info *di, uint channel, uint address, uint32 *data, bool lock )
85 		ACQUIRE_BEN( di->si->cp.lock );
87 	res = do_VIPRead( di, channel, address, data );
90 		RELEASE_BEN( di->si->cp.lock );
97 static bool do_VIPFifoRead(device_info *di, uint8 channel, uint32 address, uint32 count, uint8 *buffer)
99    	vuint8 *regs = di->regs;
111 	Radeon_WaitForFifo( di, 2);
115 	while(B_BUSY == (status = RADEON_VIPFifoIdle( di , 0xff)));
124 	Radeon_WaitForFifo( di, 2 ); // Radeon_WaitForIdle( di, false, false );
133 	Radeon_WaitForFifo( di, 2 ); // Radeon_WaitForIdle( di, false, false );
136 	while(B_BUSY == (status = RADEON_VIPFifoIdle( di , 0xff)));
141 	Radeon_WaitForFifo( di, 2 ); // Radeon_WaitForIdle( di, false, false );
147 	Radeon_WaitForFifo( di, 2 ); // Radeon_WaitForIdle( di, false, false );
160 	while(B_BUSY == (status = RADEON_VIPFifoIdle( di , 0xff)));
171 bool Radeon_VIPFifoRead(device_info *di, uint8 channel, uint32 address, uint32 count, uint8 *buffer, bool lock)
176 		ACQUIRE_BEN( di->si->cp.lock );
178 	res = do_VIPFifoRead( di, channel, address, count, buffer );
181 		RELEASE_BEN( di->si->cp.lock );
190 static bool do_VIPWrite( device_info *di, uint8 channel, uint address, uint32 data )
192 	vuint8 *regs = di->regs;
194 	Radeon_WaitForFifo( di, 2 );
197 	if( !Radeon_VIPWaitForIdle( di )) return false;
201 	Radeon_WaitForFifo( di, 2 );
204 	return Radeon_VIPWaitForIdle( di );
209 bool Radeon_VIPWrite(device_info *di, uint8 channel, uint address, uint32 data, bool lock )
216 		ACQUIRE_BEN( di->si->cp.lock );
218 	res = do_VIPWrite( di, channel, address, data );
221 		RELEASE_BEN( di->si->cp.lock );
227 static bool do_VIPFifoWrite(device_info *di, uint8 channel, uint32 address,
230 	vuint8 *regs = di->regs;
238 	Radeon_WaitForFifo( di, 2 );
243 		status = RADEON_VIPFifoIdle(di, 0x0f);
255 		Radeon_WaitForFifo( di, 2);
260 			status = RADEON_VIPFifoIdle(di, 0x0f);
273 bool Radeon_VIPFifoWrite(device_info *di, uint8 channel, uint32 address, uint32 count, uint8 *buffer, bool lock)
280 		ACQUIRE_BEN( di->si->cp.lock );
282 	Radeon_VIPReset( di, false);
283 	res = do_VIPFifoWrite( di, channel, address, count, buffer );
286 		RELEASE_BEN( di->si->cp.lock );
294 	device_info *di, bool lock )
296 	vuint8 *regs = di->regs;
299 		ACQUIRE_BEN( di->si->cp.lock );
301 	Radeon_WaitForFifo( di, 5 ); // Radeon_WaitForIdle( di, false, false );
302 	switch(di->asic){
339 		RELEASE_BEN( di->si->cp.lock );
346 	device_info *di )
348 	vuint8 *regs = di->regs;
351 	//Radeon_WaitForIdle( di, false, false );
364 static status_t RADEON_VIPFifoIdle(device_info *di, uint8 channel)
366 	vuint8 *regs = di->regs;
382 	device_info *di )
390 		res = Radeon_VIPIdle( di );
409 	device_info *di, uint32 device_id )
416 	if( !di->has_vip ) {
421 	ACQUIRE_BEN( di->si->cp.lock );
423 	Radeon_VIPReset( di, false );
429 		if( !Radeon_VIPRead( di, channel, RADEON_VIP_VENDOR_DEVICE_ID, &cur_device_id, false ))	{
438 			RELEASE_BEN( di->si->cp.lock );
443 	RELEASE_BEN( di->si->cp.lock );