graphics/radeon/mem_controller.c

9 	The memory controller of the Radeon provides a universal mapping
11 	graphics chip to addresses in local/PCI/AGP memory. Here, we
15 	means non-local memory interface).
44 	// bug in asics mean memory must be aligned to memory size...
49 	// set address range of video memory;
51 	si->memory[mt_local].virtual_addr_start = aper0;
52 	si->memory[mt_local].virtual_size = di->local_mem_size;
59 	si->memory[mt_PCI].virtual_addr_start = (getTopOfRam() + 4095) & ~4095;
60 	si->memory[mt_PCI].virtual_size = ATI_MAX_PCIGART_PAGES * ATI_PCIGART_PAGE_SIZE;
67 	si->memory[mt_AGP].virtual_addr_start =
68 		(si->memory[mt_PCI].virtual_addr_start + si->memory[mt_PCI].virtual_size
70 	si->memory[mt_AGP].virtual_size = 0x400000;
76 // graphics card addresses are mapped in a way to restrict direct main memory access
82 	// leads to a direct memory access
88 	si->memory[mt_PCI].virtual_size = ATI_MAX_PCIGART_PAGES * ATI_PCIGART_PAGE_SIZE;
89 	si->memory[mt_PCI].virtual_addr_start = 0 - si->memory[mt_PCI].virtual_size;
95 	// the memory controller won't choke if we ever access it)
96 	si->memory[mt_AGP].virtual_size = 0x400000;
97 	si->memory[mt_AGP].virtual_addr_start =
98 		si->memory[mt_PCI].virtual_addr_start -
99 		si->memory[mt_AGP].virtual_size;
101 	// set address range of video memory
104 	si->memory[mt_local].virtual_addr_start = 0;
105 	si->memory[mt_local].virtual_size =
106 		si->memory[mt_AGP].virtual_addr_start -
107 		si->memory[mt_local].virtual_addr_start;
117 	// the frame buffer memory address range is read from TOM register
120 	si->memory[mt_local].virtual_addr_start = (tom & 0xffff) << 16;
121 	si->memory[mt_local].virtual_size =
123 		si->memory[mt_local].virtual_addr_start;
125 	// after the frame buffer, physical memory should end and unused
127 	si->memory[mt_PCI].virtual_addr_start = ((((tom >> 16) + 1) << 16) + 4095) & ~4095;
128 	si->memory[mt_PCI].virtual_size = ATI_MAX_PCIGART_PAGES * ATI_PCIGART_PAGE_SIZE;
131 	si->memory[mt_AGP].virtual_addr_start =
132 		(si->memory[mt_PCI].virtual_addr_start +
133 		si->memory[mt_PCI].virtual_size + 0x3fffff) & ~0x3fffff;
134 	si->memory[mt_AGP].virtual_size = 0x400000;
149 	SHOW_INFO( 3, " local memory 0x%" B_PRIx32 "@0x%" B_PRIx32,
150 		si->memory[mt_local].virtual_size, si->memory[mt_local].virtual_addr_start );
152 		si->memory[mt_PCI].virtual_size, si->memory[mt_PCI].virtual_addr_start );
154 		si->memory[mt_AGP].virtual_size, si->memory[mt_AGP].virtual_addr_start );
167 	OUTREG( regs, RADEON_AIC_LO_ADDR, si->memory[mt_PCI].virtual_addr_start );
168 	OUTREG( regs, RADEON_AIC_HI_ADDR, si->memory[mt_PCI].virtual_addr_start +
169 		si->memory[mt_PCI].virtual_size/*di->pci_gart.buffer.size*/ - 1 );
173 		(si->memory[mt_AGP].virtual_addr_start >> 16) |
174 		((si->memory[mt_AGP].virtual_addr_start + si->memory[mt_AGP].virtual_size - 1) & 0xffff0000 )*/);
179 	// set address range of video memory
183 		((si->memory[mt_local].virtual_addr_start + si->memory[mt_local].virtual_size - 1) & 0xffff0000) |
184 		 (si->memory[mt_local].virtual_addr_start >> 16) );
187 	// (we could specify any address too, but local memory is of course first choice)
188 	OUTREG( regs, RADEON_DISPLAY_BASE_ADDRESS, si->memory[mt_local].virtual_addr_start );
189 	OUTREG( regs, RADEON_CRTC2_DISPLAY_BASE_ADDRESS, si->memory[mt_local].virtual_addr_start );
190 	OUTREG( regs, RADEON_OV0_BASE_ADDRESS, si->memory[mt_local].virtual_addr_start );