graphics/radeon/irq.c

19 Radeon_DisableIRQ(device_info *di)
21 	OUTREG(di->regs, RADEON_GEN_INT_CNTL, 0);
30 Radeon_ThreadInterruptWork(vuint8 *regs, device_info *di, uint32 int_status)
32 	shared_info *si = di->si;
39 		++di->vbi_count[0];
51 		++di->vbi_count[1];
60 		release_sem_etc(di->dma_sem, 1, B_DO_NOT_RESCHEDULE);
71 Radeon_HandleCaptureInterrupt(vuint8 *regs, device_info *di, uint32 cap_status)
77 	acquire_spinlock(&di->cap_spinlock);
79 	++di->cap_counter;
80 	di->cap_int_status = cap_status;
81 	di->cap_timestamp = system_time();
83 	release_spinlock(&di->cap_spinlock);
87 	if (get_sem_count(di->cap_sem, &blocked) == B_OK && blocked <= 0) {
88 		release_sem_etc(di->cap_sem, 1, B_DO_NOT_RESCHEDULE);
105 	device_info *di = (device_info *)data;
106 	vuint8 *regs = di->regs;
114 		++di->interrupt_count;
116 		handled = Radeon_ThreadInterruptWork(regs, di, int_status);
134 			cap_handled = Radeon_HandleCaptureInterrupt(regs, di, cap_status);
152 	device_info *di = ((timer_info *)te)->di;
153 	shared_info *si = di->si;
154 	vuint8 *regs = di->regs;
159 	if (!di->shutdown_virtual_irq) {
171 			result = Radeon_ThreadInterruptWork(regs, di,
173 				| (di->num_crtc > 1 ? RADEON_CRTC2_VBLANK_STAT : 0));
177 		to = (timer *)&di->ti_a;
179 			to = (timer *)&di->ti_b;
189 		di->current_timer = (timer_info *)to;
202 Radeon_SetupIRQ(device_info *di, char *buffer)
204 	shared_info *si = di->si;
210 		di->pcii.vendor_id, di->pcii.device_id,
211 		di->pcii.bus, di->pcii.device, di->pcii.function);
220 	if (di->num_crtc > 1) {
222 			di->pcii.vendor_id, di->pcii.device_id,
223 			di->pcii.bus, di->pcii.device, di->pcii.function);
232 		di->pcii.vendor_id, di->pcii.device_id,
233 		di->pcii.bus, di->pcii.device, di->pcii.function);
234 	di->cap_sem = create_sem(0, buffer);
235 	if (di->cap_sem < 0) {
236 		result = di->cap_sem;
240 	B_INITIALIZE_SPINLOCK(&di->cap_spinlock);
243 		di->pcii.vendor_id, di->pcii.device_id,
244 		di->pcii.bus, di->pcii.device, di->pcii.function);
245 	di->dma_sem = create_sem(0, buffer);
246 	if (di->dma_sem < 0) {
247 		result = di->dma_sem;
256 	if (di->num_crtc > 1)
258 	//set_sem_owner(di->cap_sem, thinfo.team);
261 	Radeon_DisableIRQ(di);
264 	if (di->pcii.u.h0.interrupt_pin == 0x00 || di->pcii.u.h0.interrupt_line == 0xff) {
267 		di->shutdown_virtual_irq = false;
271 		di->ti_a.di = di;    /* refer to ourself */
272 		di->ti_b.di = di;
273 		di->current_timer = &di->ti_a;
276 		result = add_timer((timer *)(di->current_timer), timer_interrupt_func,
282 		result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line,
283 			Radeon_Interrupt, (void *)di, 0);
287 		SHOW_INFO(3, "installed IRQ @ %d", di->pcii.u.h0.interrupt_line);
293 	delete_sem(di->dma_sem);
295 	delete_sem(di->cap_sem);
297 	if (di->num_crtc > 1)
309 Radeon_CleanupIRQ(device_info *di)
311 	shared_info *si = di->si;
313 	Radeon_DisableIRQ(di);
316 	if (di->pcii.u.h0.interrupt_pin == 0x00 || di->pcii.u.h0.interrupt_line == 0xff) {
318 		di->shutdown_virtual_irq = true;
321 		cancel_timer((timer *)&di->ti_a);
322 		cancel_timer((timer *)&di->ti_b);
325 		remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, Radeon_Interrupt, di);
330 	if (di->num_crtc > 1)
333 	delete_sem(di->cap_sem);
334 	delete_sem(di->dma_sem);
336 	di->cap_sem = si->crtc[1].vblank = si->crtc[0].vblank = 0;