Lines Matching refs:di
32 #define RADEON_BIOS8(v) (di->rom.rom_ptr[v])
33 #define RADEON_BIOS16(v) ((di->rom.rom_ptr[v]) | \
34 (di->rom.rom_ptr[(v) + 1] << 8))
35 #define RADEON_BIOS32(v) ((di->rom.rom_ptr[v]) | \
36 (di->rom.rom_ptr[(v) + 1] << 8) | \
37 (di->rom.rom_ptr[(v) + 2] << 16) | \
38 (di->rom.rom_ptr[(v) + 3] << 24))
118 static void Radeon_GetPLLInfo( device_info *di )
124 bios_header = di->rom.rom_ptr + *(uint16 *)(di->rom.rom_ptr + 0x48);
125 pll_info = (PLL_BLOCK *)(di->rom.rom_ptr + *(uint16 *)(bios_header + 0x30));
144 di->is_atombios = true;
150 di->pll.ref_div = 0;
151 di->pll.max_pll_freq = RADEON_BIOS16(pll_start + 32);
152 di->pll.xclk = RADEON_BIOS16(pll_start + 72);
153 di->pll.min_pll_freq = RADEON_BIOS16(pll_start + 78);
154 di->pll.ref_freq = RADEON_BIOS16(pll_start + 82);
159 di->pll.ref_freq, di->pll.ref_div, di->pll.xclk,
160 di->pll.min_pll_freq, di->pll.max_pll_freq );
171 di->is_atombios = false;
175 di->pll.xclk = (uint32)pll.XCLK;
176 di->pll.ref_freq = (uint32)pll.PCLK_ref_freq;
177 di->pll.ref_div = (uint32)pll.PCLK_ref_divider;
178 di->pll.min_pll_freq = pll.PCLK_min_freq;
179 di->pll.max_pll_freq = pll.PCLK_max_freq;
184 di->pll.ref_freq, di->pll.ref_div, di->pll.xclk,
185 di->pll.min_pll_freq, di->pll.max_pll_freq );
205 static void Radeon_GetMonType( device_info *di )
211 di->disp_type[0] = di->disp_type[1] = dt_none;
213 if (di->has_crtc2) {
214 tmp = INREG( di->regs, RADEON_BIOS_4_SCRATCH );
223 di->disp_type[0] = dt_dvi;
225 di->disp_type[0] = dt_lvds;
227 di->disp_type[0] = dt_tv_crt;
229 di->disp_type[0] = dt_ctv;
231 di->disp_type[0] = dt_stv;
237 di->disp_type[1] = dt_ctv;
239 di->disp_type[1] = dt_stv;
241 di->disp_type[1] = dt_crt;
243 di->disp_type[1] = dt_dvi_ext;
246 di->disp_type[1] = dt_lvds;
250 di->disp_type[0] = dt_none;
252 tmp = INREG( di->regs, RADEON_FP_GEN_CNTL);
255 di->disp_type[0] = dt_dvi;
257 di->disp_type[0] = dt_crt;
261 Mon2Str[di->disp_type[0]], Mon2Str[di->disp_type[1]]);
264 if( di->disp_type[0] >= dt_dvi_ext )
265 di->disp_type[0] = dt_none;
266 if( di->disp_type[1] >= dt_dvi_ext )
267 di->disp_type[1] = dt_none;
273 if( di->has_crtc2 ) {
274 if( di->disp_type[0] == dt_none && di->disp_type[1] == dt_crt ) {
275 di->disp_type[0] = dt_crt;
276 di->disp_type[1] = dt_none;
281 Mon2Str[di->disp_type[0]], Mon2Str[di->disp_type[1]]);
286 static bool Radeon_GetConnectorInfoFromBIOS ( device_info* di )
289 ptr_disp_entity ptr_entity = &di->routing;
296 if (di->is_atombios)
435 if (di->is_mobility)
505 static bool Radeon_GetBIOSDFPInfo( device_info *di )
517 if (di->is_atombios)
526 di->fp_info.panel_xres = RADEON_BIOS16( tmp + 6 );
527 di->fp_info.panel_yres = RADEON_BIOS16( tmp + 10 );
528 di->fp_info.dot_clock = RADEON_BIOS16( tmp + 4 ) * 10;
529 di->fp_info.h_blank = RADEON_BIOS16( tmp + 8 );
530 di->fp_info.h_over_plus = RADEON_BIOS16( tmp + 14 );
531 di->fp_info.h_sync_width = RADEON_BIOS16( tmp + 16 );
532 di->fp_info.v_blank = RADEON_BIOS16( tmp + 12 );
533 di->fp_info.v_over_plus = RADEON_BIOS16( tmp + 18 );
534 di->fp_info.h_sync_width = RADEON_BIOS16( tmp + 20 );
535 di->fp_info.panel_pwr_delay = RADEON_BIOS16( tmp + 40 );
542 di->fp_info.panel_xres, di->fp_info.panel_yres, di->fp_info.dot_clock,
543 di->fp_info.h_blank, di->fp_info.h_over_plus, di->fp_info.h_sync_width,
544 di->fp_info.v_blank, di->fp_info.v_over_plus, di->fp_info.h_sync_width,
545 di->fp_info.panel_pwr_delay );
550 di->fp_info.panel_pwr_delay = 200;
561 di->fp_info.panel_pwr_delay = 200;
566 memcpy( &fpi, di->rom.rom_ptr + fpi_offset, sizeof( fpi ));
573 di->fp_info.panel_xres = fpi.panel_xres;
574 di->fp_info.panel_yres = fpi.panel_yres;
577 di->fp_info.panel_xres, di->fp_info.panel_yres);
579 di->fp_info.panel_pwr_delay = fpi.panel_pwr_delay;
580 if( di->fp_info.panel_pwr_delay > 2000 || di->fp_info.panel_pwr_delay < 0 )
581 di->fp_info.panel_pwr_delay = 2000;
583 di->fp_info.ref_div = fpi.ref_div;
584 di->fp_info.post_div = fpi.post_div;
585 di->fp_info.feedback_div = fpi.feedback_div;
587 di->fp_info.fixed_dividers =
588 di->fp_info.ref_div != 0 && di->fp_info.feedback_div > 3;
602 memcpy( &fpi_timing, di->rom.rom_ptr + fpi_timing_ofs, sizeof( fpi_timing ));
604 if( fpi_timing.panel_xres != di->fp_info.panel_xres ||
605 fpi_timing.panel_yres != di->fp_info.panel_yres )
608 di->fp_info.h_blank = (fpi_timing.h_total - fpi_timing.h_display) * 8;
610 di->fp_info.h_over_plus = ((fpi_timing.h_sync_start & 0xfff) - fpi_timing.h_display - 1) * 8;
611 di->fp_info.h_sync_width = fpi_timing.h_sync_width * 8;
612 di->fp_info.v_blank = fpi_timing.v_total - fpi_timing.v_display;
613 di->fp_info.v_over_plus = (fpi_timing.v_sync & 0x7ff) - fpi_timing.v_display;
614 di->fp_info.v_sync_width = (fpi_timing.v_sync & 0xf800) >> 11;
615 di->fp_info.dot_clock = fpi_timing.dot_clock * 10;
629 static void Radeon_RevEnvDFPSize( device_info *di )
631 vuint8 *regs = di->regs;
633 di->fp_info.panel_yres =
637 di->fp_info.panel_xres =
642 di->fp_info.panel_xres, di->fp_info.panel_yres);
647 static void Radeon_RevEnvDFPTiming( device_info *di )
649 vuint8 *regs = di->regs;
658 di->fp_info.h_blank = (a - b) * 8;
663 di->fp_info.h_over_plus =
666 di->fp_info.h_over_plus *= 8;
667 di->fp_info.h_sync_width =
672 di->fp_info.h_sync_width *= 8;
677 di->fp_info.v_blank = a - b;
682 di->fp_info.v_over_plus = (r & RADEON_FP_V_SYNC_STRT_MASK) - b;
683 di->fp_info.v_sync_width = ((r & RADEON_FP_V_SYNC_WID_MASK)
690 di->fp_info.h_blank = (a - b) * 8;
695 di->fp_info.h_over_plus =
698 di->fp_info.h_over_plus *= 8;
699 di->fp_info.h_sync_width =
702 di->fp_info.h_sync_width *= 8;
707 di->fp_info.v_blank = a - b;
712 di->fp_info.v_over_plus = (r & RADEON_CRTC_V_SYNC_STRT) - b;
713 di->fp_info.v_sync_width = ((r & RADEON_CRTC_V_SYNC_WID)
718 static void Radeon_GetTMDSInfoFromBios( device_info *di )
728 di->tmds_pll[i].value = 0;
729 di->tmds_pll[i].freq = 0;
732 if (di->is_atombios)
742 di->tmds_pll[i].freq = RADEON_BIOS16(tmp + i * 6 + 6);
744 di->tmds_pll[i].value = ((RADEON_BIOS8(tmp + i * 6 + 8) & 0x3f) |
749 di->tmds_pll[i].freq, di->tmds_pll[i].value);
751 if (maxfreq == di->tmds_pll[i].freq) {
752 di->tmds_pll[i].freq = 0xffffffff;
768 di->tmds_pll[i].value = RADEON_BIOS32(tmp + i * 10 + 0x08);
769 di->tmds_pll[i].freq = RADEON_BIOS16(tmp + i * 10 + 0x10);
778 di->tmds_pll[i].value = RADEON_BIOS32(tmp + stride + 0x08);
779 di->tmds_pll[i].freq = RADEON_BIOS16(tmp + stride + 0x10);
796 di->tmds_pll[i].value = RADEON_BIOS32(tmp + stride + 0x08);
797 di->tmds_pll[i].freq = RADEON_BIOS16(tmp + stride + 0x10);
812 di->tmds_pll[i].value = default_tmds_pll[di->asic][i].value;
813 di->tmds_pll[i].freq = default_tmds_pll[di->asic][i].freq;
815 di->tmds_pll[i].freq, di->tmds_pll[i].value);
822 static void Radeon_GetBIOSMon( device_info *di )
824 Radeon_GetMonType( di );
828 memset( &di->fp_info, 0, sizeof( di->fp_info ));
831 di->fp_info.disp_type = di->disp_type[0];
833 if( di->is_mobility ) {
835 Radeon_GetBIOSDFPInfo( di );
838 if( di->fp_info.panel_xres == 0 || di->fp_info.panel_yres == 0)
839 Radeon_RevEnvDFPSize( di );
841 if( di->fp_info.h_blank == 0 || di->fp_info.v_blank == 0)
842 Radeon_RevEnvDFPTiming( di );
845 di->fp_info.panel_xres, di->fp_info.h_blank, di->fp_info.h_over_plus, di->fp_info.h_sync_width );
847 di->fp_info.panel_yres, di->fp_info.v_blank, di->fp_info.v_over_plus, di->fp_info.v_sync_width );
848 SHOW_INFO( 2, "pixel_clock=%d", di->fp_info.dot_clock );
854 static void Radeon_GetFPData( device_info *di )
858 memset( &di->fp_info, 0, sizeof( di->fp_info ));
861 if( !di->is_mobility )
865 Radeon_GetBIOSDFPInfo( di );
868 if( di->fp_info.panel_xres == 0 || di->fp_info.panel_yres == 0)
869 Radeon_RevEnvDFPSize( di );
871 if( di->fp_info.h_blank == 0 || di->fp_info.v_blank == 0)
872 Radeon_RevEnvDFPTiming( di );
875 di->fp_info.panel_xres, di->fp_info.h_blank, di->fp_info.h_over_plus, di->fp_info.h_sync_width );
877 di->fp_info.panel_yres, di->fp_info.v_blank, di->fp_info.v_over_plus, di->fp_info.v_sync_width );
878 SHOW_INFO( 2, "pixel_clock=%d", di->fp_info.dot_clock );
885 static uint32 RADEON_GetAccessibleVRAM( device_info *di )
887 vuint8 *regs = di->regs;
888 pci_info *pcii = &(di->pcii);
894 if (di->asic == rt_rv280 ||
895 di->asic == rt_rv350 ||
896 di->asic == rt_rv380 ||
897 di->asic == rt_r420 ) {
924 static void Radeon_DetectRAM( device_info *di )
926 vuint8 *regs = di->regs;
929 if( di->is_igp ) {
933 di->local_mem_size = ((tom >> 16) + 1 - (tom & 0xffff)) << 16;
934 OUTREG( regs, RADEON_CONFIG_MEMSIZE, di->local_mem_size * 1024);
936 di->local_mem_size = INREG( regs, RADEON_CONFIG_MEMSIZE ) & RADEON_CONFIG_MEMSIZE_MASK;
940 if( di->local_mem_size == 0 ) {
941 di->local_mem_size = 8 * 1024 *1024;
942 OUTREG( regs, RADEON_CONFIG_MEMSIZE, di->local_mem_size);
947 accessible = RADEON_GetAccessibleVRAM( di );
950 bar_size = di->pcii.u.h0.base_register_sizes[0];
960 di->local_mem_size / 1024,
963 if (di->local_mem_size > accessible)
964 di->local_mem_size = accessible;
971 case 0: di->ram.width = 64; break;
972 case 1: di->ram.width = 128; break;
973 case 2: di->ram.width = 256; break;
974 default: di->ram.width = 128; break;
976 } else if ( (di->asic >= rt_rv100) ||
977 (di->asic >= rt_rs100) ||
978 (di->asic >= rt_rs200)) {
980 di->ram.width = 32;
982 di->ram.width = 64;
985 di->ram.width = 128;
987 di->ram.width = 64;
990 if (di->is_igp || (di->asic >= rt_r300))
995 strcpy(di->ram_type, "SDR SGRAM");
996 di->ram.ml = 4;
997 di->ram.MB = 4;
998 di->ram.Trcd = 1;
999 di->ram.Trp = 2;
1000 di->ram.Twr = 1;
1001 di->ram.CL = 2;
1002 di->ram.loop_latency = 16;
1003 di->ram.Rloop = 16;
1004 di->ram.Tr2w = 0;
1007 strcpy(di->ram_type, "DDR SGRAM");
1008 di->ram.ml = 4;
1009 di->ram.MB = 4;
1010 di->ram.Trcd = 3;
1011 di->ram.Trp = 3;
1012 di->ram.Twr = 2;
1013 di->ram.CL = 3;
1014 di->ram.Tr2w = 1;
1015 di->ram.loop_latency = 16;
1016 di->ram.Rloop = 16;
1021 di->local_mem_size / 1024 / 1024, di->ram_type, di->ram.width);
1023 /* if( di->local_mem_size > 64 * 1024 * 1024 ) {
1024 di->local_mem_size = 64 * 1024 * 1024;
1076 status_t Radeon_ReadBIOSData( device_info *di )
1082 di->si = &dummy_si;
1085 result = Radeon_MapDevice( di, true );
1089 Radeon_GetPLLInfo( di );
1092 di->routing.port_info[0].mon_type = mt_unknown;
1093 di->routing.port_info[0].ddc_type = ddc_none_detected;
1094 di->routing.port_info[0].dac_type = dac_unknown;
1095 di->routing.port_info[0].tmds_type = tmds_unknown;
1096 di->routing.port_info[0].connector_type = connector_none;
1098 di->routing.port_info[1].mon_type = mt_unknown;
1099 di->routing.port_info[1].ddc_type = ddc_none_detected;
1100 di->routing.port_info[1].dac_type = dac_unknown;
1101 di->routing.port_info[1].tmds_type = tmds_unknown;
1102 di->routing.port_info[1].connector_type = connector_none;
1104 if ( !Radeon_GetConnectorInfoFromBIOS( di ) )
1106 di->routing.port_info[0].mon_type = mt_unknown;
1107 di->routing.port_info[0].ddc_type = ddc_none_detected;
1108 di->routing.port_info[0].dac_type = dac_tvdac;
1109 di->routing.port_info[0].tmds_type = tmds_unknown;
1110 di->routing.port_info[0].connector_type = connector_proprietary;
1112 di->routing.port_info[1].mon_type = mt_unknown;
1113 di->routing.port_info[1].ddc_type = ddc_none_detected;
1114 di->routing.port_info[1].dac_type = dac_primary;
1115 di->routing.port_info[1].tmds_type = tmds_ext;
1116 di->routing.port_info[1].connector_type = connector_crt;
1119 Radeon_GetFPData( di );
1120 Radeon_GetTMDSInfoFromBios( di );
1121 Radeon_DetectRAM( di );
1123 Radeon_UnmapDevice( di );
1126 di->si = NULL;