graphics/radeon/DMA.c

24 status_t Radeon_InitDMA( device_info *di )
30 	di->dma_desc_max_num = RADEON_MAX_DMA_SIZE / 4096;
32 	res = mem_alloc( di->memmgr[mt_local], di->dma_desc_max_num * sizeof( DMA_descriptor ), 0,
33 		&di->dma_desc_handle, &di->dma_desc_offset );
39 	OUTREGP( di->regs, RADEON_GEN_INT_CNTL, RADEON_VIDDMA_MASK, ~RADEON_VIDDMA_MASK );
41 	OUTREG( di->regs, RADEON_GEN_INT_STATUS, RADEON_VIDDMA_AK );
49 	device_info *di, uint32 src, char *target, size_t size, bool lock_mem, bool contiguous )
66 	src += di->si->memory[mt_local].virtual_addr_start;
68 	cur_desc = (DMA_descriptor *)(di->si->local_mem + di->dma_desc_offset);
107 				if( ++num_desc > (int)di->dma_desc_max_num ) {
143 	device_info *di, uint32 src, char *target, size_t size, bool lock_mem, bool contiguous )
157 	device_info *di, uint32 src, char *target, size_t size, bool lock_mem, bool contiguous )
164 	res =  Radeon_PrepareDMA( di, src, target, size, lock_mem, contiguous );
170 	OUTREG( di->regs, RADEON_DMA_VID_TABLE_ADDR, di->si->memory[mt_local].virtual_addr_start +
171 		di->dma_desc_offset );
173 	res = acquire_sem_etc( di->dma_sem, 1, B_RELATIVE_TIMEOUT, 1000000 );
176 	while( (INREG( di->regs, RADEON_DMA_VID_STATUS ) & RADEON_DMA_STATUS_ACTIVE) != 0 ) {
181 	Radeon_FinishDMA( di, src, target, size, lock_mem, contiguous );