graphics/radeon/CP_setup.c

644     uint32 tmp;
649 			tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);
650 			tmp |= (RADEON_SCLK_FORCE_CP   | RADEON_SCLK_FORCE_HDP |
657 			Radeon_OUTPLL(regs, asic, RADEON_SCLK_CNTL, tmp);
660 			tmp = Radeon_INPLL(regs, asic, R300_SCLK_CNTL2);
661 			tmp |= (R300_SCLK_FORCE_TCL |
664 			Radeon_OUTPLL(regs, asic, R300_SCLK_CNTL2, tmp);
666 			tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);
667 			tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP      |
675 			Radeon_OUTPLL(regs, asic, RADEON_SCLK_CNTL, tmp);
677 			tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_MORE_CNTL);
678 			tmp |= RADEON_SCLK_MORE_FORCEON;
679 			Radeon_OUTPLL(regs, asic, RADEON_SCLK_MORE_CNTL, tmp);
681 			tmp = Radeon_INPLL(regs, asic, RADEON_MCLK_CNTL);
682 			tmp |= (RADEON_FORCEON_MCLKA |
687 			Radeon_OUTPLL(regs, asic, RADEON_MCLK_CNTL, tmp);
689 			tmp = Radeon_INPLL(regs, asic, RADEON_VCLK_ECP_CNTL);
690 			tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb  |
693 			Radeon_OUTPLL(regs, asic, RADEON_VCLK_ECP_CNTL, tmp);
695 			tmp = Radeon_INPLL(regs, asic, RADEON_PIXCLKS_CNTL);
696 			tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb         |
710 			Radeon_OUTPLL(regs, asic, RADEON_PIXCLKS_CNTL, tmp);
712 			tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);
713 			tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2);
714 			tmp |= RADEON_SCLK_FORCE_SE;
717 				tmp |= ( RADEON_SCLK_FORCE_RB    |
729 				tmp |= ( RADEON_SCLK_FORCE_HDP   |
736 			Radeon_OUTPLL(regs, asic, RADEON_SCLK_CNTL, tmp);
741 				tmp = Radeon_INPLL(regs, asic, R300_SCLK_CNTL2);
742 				tmp |= ( R300_SCLK_FORCE_TCL |
745 				Radeon_OUTPLL(regs, asic, R300_SCLK_CNTL2, tmp);
750 				tmp = Radeon_INPLL(regs, asic, RADEON_MCLK_CNTL);
751 				tmp &= ~(RADEON_FORCEON_MCLKA |
753 				Radeon_OUTPLL(regs, asic, RADEON_MCLK_CNTL, tmp);
760 				tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_MORE_CNTL);
761 				tmp |= RADEON_SCLK_MORE_FORCEON;
762 				Radeon_OUTPLL(regs, asic, RADEON_SCLK_MORE_CNTL, tmp);
766 			tmp = Radeon_INPLL(regs, asic, RADEON_PIXCLKS_CNTL);
767 			tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb         |
775 			Radeon_OUTPLL(regs, asic, RADEON_PIXCLKS_CNTL, tmp);
778 			tmp = Radeon_INPLL(regs, asic, RADEON_VCLK_ECP_CNTL);
779 			tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb  |
781 			Radeon_OUTPLL(regs, asic, RADEON_VCLK_ECP_CNTL, tmp);
787 			tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);
789 				tmp &= ~(RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_RB);
791 			tmp &= ~(RADEON_SCLK_FORCE_HDP  | RADEON_SCLK_FORCE_DISP1 |
796 			Radeon_OUTPLL(regs, asic, RADEON_SCLK_CNTL, tmp);
801 				tmp = Radeon_INPLL(regs, asic, R300_SCLK_CNTL2);
802 				tmp &= ~(R300_SCLK_FORCE_TCL |
805 				tmp |=  (R300_SCLK_TCL_MAX_DYN_STOP_LAT |
808 				Radeon_OUTPLL(regs, asic, R300_SCLK_CNTL2, tmp);
810 				tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);
811 				tmp &= ~(RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP      |
819 					tmp |=  RADEON_DYN_STOP_LAT_MASK;
820 				Radeon_OUTPLL(regs, asic, RADEON_SCLK_CNTL, tmp);
822 				tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_MORE_CNTL);
823 				tmp &= ~RADEON_SCLK_MORE_FORCEON;
824 				tmp |=  RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
825 				Radeon_OUTPLL(regs, asic, RADEON_SCLK_MORE_CNTL, tmp);
827 				tmp = Radeon_INPLL(regs, asic, RADEON_VCLK_ECP_CNTL);
828 				tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
830 				Radeon_OUTPLL(regs, asic, RADEON_VCLK_ECP_CNTL, tmp);
832 				tmp = Radeon_INPLL(regs, asic, RADEON_PIXCLKS_CNTL);
833 				tmp |= (RADEON_PIX2CLK_ALWAYS_ONb         |
846 				Radeon_OUTPLL(regs, asic, RADEON_PIXCLKS_CNTL, tmp);
848 				tmp = Radeon_INPLL(regs, asic, RADEON_MCLK_MISC);
849 				tmp |= (RADEON_MC_MCLK_DYN_ENABLE |
851 				Radeon_OUTPLL(regs, asic, RADEON_MCLK_MISC, tmp);
853 				tmp = Radeon_INPLL(regs, asic, RADEON_MCLK_CNTL);
854 				tmp |= (RADEON_FORCEON_MCLKA |
857 				tmp &= ~(RADEON_FORCEON_YCLKA  |
865 				if ((tmp & R300_DISABLE_MC_MCLKA) &&
866 				(tmp & R300_DISABLE_MC_MCLKB)) {
868 					tmp = Radeon_INPLL(regs, asic, RADEON_MCLK_CNTL);
871 						tmp &= ~R300_DISABLE_MC_MCLKB;
873 						tmp &= ~R300_DISABLE_MC_MCLKA;
875 						tmp &= ~(R300_DISABLE_MC_MCLKA |
880 				Radeon_OUTPLL(regs, asic, RADEON_MCLK_CNTL, tmp);
882 				tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);
883 				tmp &= ~(R300_SCLK_FORCE_VAP);
884 				tmp |= RADEON_SCLK_FORCE_CP;
885 				Radeon_OUTPLL(regs, asic, RADEON_SCLK_CNTL, tmp);
888 				tmp = Radeon_INPLL(regs, asic, R300_SCLK_CNTL2);
889 				tmp &= ~(R300_SCLK_FORCE_TCL |
892 				Radeon_OUTPLL(regs, asic, R300_SCLK_CNTL2, tmp);
895 			tmp = Radeon_INPLL(regs, asic, RADEON_CLK_PWRMGT_CNTL);
897 			tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK     |
901 			tmp |= (RADEON_ENGIN_DYNCLK_MODE |
903 			Radeon_OUTPLL(regs, asic, RADEON_CLK_PWRMGT_CNTL, tmp);
906 			tmp = Radeon_INPLL(regs, asic, RADEON_CLK_PIN_CNTL);
907 			tmp |= RADEON_SCLK_DYN_START_CNTL;
908 			Radeon_OUTPLL(regs, asic, RADEON_CLK_PIN_CNTL, tmp);
914 			tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);
915 			/*tmp &= RADEON_SCLK_SRC_SEL_MASK;*/
916 			tmp &= ~RADEON_SCLK_FORCEON_MASK;
926 				tmp |= RADEON_SCLK_FORCE_CP;
927 				tmp |= RADEON_SCLK_FORCE_VIP;
930 			Radeon_OUTPLL(regs, asic, RADEON_SCLK_CNTL, tmp);
935 				tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_MORE_CNTL);
936 				tmp &= ~RADEON_SCLK_MORE_FORCEON;
944 					tmp |= RADEON_SCLK_MORE_FORCEON;
946 				Radeon_OUTPLL(regs, asic, RADEON_SCLK_MORE_CNTL, tmp);
956 				tmp = Radeon_INPLL(regs, asic, RADEON_PLL_PWRMGT_CNTL);
957 				tmp |= RADEON_TCL_BYPASS_DISABLE;
958 				Radeon_OUTPLL(regs, asic, RADEON_PLL_PWRMGT_CNTL, tmp);
963 			tmp = Radeon_INPLL(regs, asic, RADEON_PIXCLKS_CNTL);
964 			tmp |=  (RADEON_PIX2CLK_ALWAYS_ONb         |
972 			Radeon_OUTPLL(regs, asic, RADEON_PIXCLKS_CNTL, tmp);
975 			tmp = Radeon_INPLL(regs, asic, RADEON_VCLK_ECP_CNTL);
976 			tmp |= (RADEON_PIXCLK_ALWAYS_ONb  |
979 			Radeon_OUTPLL(regs, asic, RADEON_VCLK_ECP_CNTL, tmp);